Yu Pu

According to our database1, Yu Pu authored at least 38 papers between 2006 and 2021.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.



In proceedings 
PhD thesis 


On csauthors.net:


0.5-1-V, 90-400-mA, Modular, Distributed, 3 × 3 Digital LDOs Based on Event-Driven Control and Domino Sampling and Regulation.
IEEE J. Solid State Circuits, 2021

Detection of the interictal epileptic discharges based on wavelet bispectrum interaction and recurrent neural network.
Sci. China Inf. Sci., 2021

Catena: A Near-Threshold, Sub-0.4-mW, 16-Core Programmable Spatial Array Accelerator for the Ultralow-Power Mobile and Embedded Internet of Things.
IEEE J. Solid State Circuits, 2020

Patient-Specific ECG Classification with Integrated Long Short-Term Memory and Convolutional Neural Networks.
IEICE Trans. Inf. Syst., 2020

Robust QRS Detection Using High-Resolution Wavelet Packet Decomposition and Time-Attention Convolutional Neural Network.
IEEE Access, 2020

A Lossless Electrocardiogram Compression System Based on Dual-Mode Prediction and Error Modeling.
IEEE Access, 2020

Energy-Efficient Arbitrary Precision Multi-Bit Multiplication with Bi-Serial In/Near Memory Computing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Xuantie-910: A Commercial Multi-Core 12-Stage Pipeline Out-of-Order 64-bit High Performance RISC-V Processor with Vector Extension : Industrial Product.
Proceedings of the 47th ACM/IEEE Annual International Symposium on Computer Architecture, 2020

Xuantie-910: Innovating Cloud and Edge Computing by RISC-V.
Proceedings of the IEEE Hot Chips 32 Symposium, 2020

A Neural Network-Based ECG Classification Processor With Exploitation of Heartbeat Similarity.
IEEE Access, 2019

Automated Heartbeat Classification Exploiting Convolutional Neural Network With Channel-Wise Attention.
IEEE Access, 2019

A 0.5-1V Input Event-Driven Multiple Digital Low-Dropout-Regulator System for Supporting a Large Digital Load.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

Catena: A 0.5-V Sub-0.4-mW 16-Core Spatial Array Accelerator for Mobile and Embedded Computing.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

VaultIME: Regaining User Control for Password Managers through Auto-correction.
EAI Endorsed Trans. Security Safety, 2018

A 9-mm<sup>2</sup> Ultra-Low-Power Highly Integrated 28-nm CMOS SoC for Internet of Things.
IEEE J. Solid State Circuits, 2018

An Ultra-low-power 28nm CMOS Dual-die ASIC Platform for Smart Hearables.
Proceedings of the 2018 IEEE Biomedical Circuits and Systems Conference, 2018

Valuating Friends' Privacy: Does Anonymity of Sharing Personal Data Matter?
Proceedings of the Thirteenth Symposium on Usable Privacy and Security, 2017

Blackghost: An ultra-low-power all-in-one 28nm CMOS SoC for Internet-of-Things.
Proceedings of the 2017 IEEE Symposium in Low-Power and High-Speed Chips, 2017

Towards a Model on the Factors Influencing Social App Users' Valuation of Interdependent Privacy.
Proc. Priv. Enhancing Technol., 2016

Sharing Is Caring, or Callous?
Proceedings of the Cryptology and Network Security - 15th International Conference, 2016

Ultra-low-energy adiabatic dynamic logic circuits using nanoelectromechanical switches.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Using Conjoint Analysis to Investigate the Value of Interdependent Privacy in Social App Adoption Scenarios.
Proceedings of the International Conference on Information Systems, 2015

Digital Systems Power Management for High Performance Mixed Signal Platforms.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014

An Economic Model and Simulation Results of App Adoption Decisions on Networks with Interdependent Privacy Consequences.
Proceedings of the Decision and Game Theory for Security - 5th International Conference, 2014

Logic synthesis of low-power ICs with ultra-wide voltage and frequency scaling.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Modelling NEM relays for digital circuit applications.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

A 1-V-Input Switched-Capacitor Voltage Converter With Voltage-Reference-Free Pulse-Density Modulation.
IEEE Trans. Circuits Syst. II Express Briefs, 2012

24% Power reduction by post-fabrication dual supply voltage control of 64 voltage domains in V<sub>DDmin</sub> limited ultra low voltage logic circuits.
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

From Xetal-II to Xetal-Pro: On the Road Toward an Ultralow-Energy and High-Throughput SIMD Processor.
IEEE Trans. Circuits Syst. Video Technol., 2011

Post-Silicon Clock Deskew Employing Hot-Carrier Injection Trimming With On-Chip Skew Monitoring and Auto-Stressing Scheme for Sub/Near Threshold Digital Circuits.
IEEE Trans. Circuits Syst. II Express Briefs, 2011

A Variable Output Voltage Switched-Capacitor DC-DC Converter with Pulse Density and Width Modulation (PDWM) for 57% Ripple Reduction at Low Output Voltage.
IEICE Trans. Electron., 2011

An Ultra-Low-Energy Multi-Standard JPEG Co-Processor in 65 nm CMOS With Sub/Near Threshold Supply Voltage.
IEEE J. Solid State Circuits, 2010

Misleading energy and performance claims in sub/near threshold digital systems.
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

Xetal-Pro: an ultra-low energy and high throughput SIMD processor.
Proceedings of the 47th Design Automation Conference, 2010

An ultra-low-energy/frame multi-standard JPEG co-processor in 65nm CMOS with sub/near-threshold power supply.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

Statistical noise margin estimation for sub-threshold combinational circuits.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

V<sub>t</sub> balancing and device sizing towards high yield of sub-threshold static logic gates.
Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007

An automated, efficient and static bit-width optimization methodology towards maximum bit-width-to-error tradeoff with affine arithmetic model.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006