Tiberiu Chelcea

According to our database1, Tiberiu Chelcea authored at least 13 papers between 2000 and 2008.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2008
Heterogeneous Latch-Based Asynchronous Pipelines.
Proceedings of the 14th IEEE International Symposium on Asynchronous Circuits and Systems, 2008

2007
Global Critical Path: A Tool for System-Level Timing Analysis.
Proceedings of the 44th Design Automation Conference, 2007

Self-Resetting Latches for Asynchronous Micro-Pipelines.
Proceedings of the 44th Design Automation Conference, 2007

Area Optimizations for Dual-Rail Circuits Using Relative-Timing Analysis.
Proceedings of the 13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2007), 2007

2006
Hardware compilation of application-specific memory-access interconnect.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Tartan: evaluating spatial computation for whole program execution.
Proceedings of the 12th International Conference on Architectural Support for Programming Languages and Operating Systems, 2006

2005
SOMA: a tool for synthesizing and optimizing memory accesses in ASICs.
Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2005

2004
Robust interfaces for mixed-timing systems.
IEEE Trans. Very Large Scale Integr. Syst., 2004

Spatial computation.
Proceedings of the 11th International Conference on Architectural Support for Programming Languages and Operating Systems, 2004

2002
Resynthesis and Peephole Transformations for the Optimization of Large-Scale Asynchronous Systems.
Proceedings of the 11th IEEE/ACM International Workshop on Logic & Synthesis, 2002

A Burst-Mode Oriented Back-End for the Balsa Synthesis System.
Proceedings of the 2002 Design, 2002

2001
Robust Interfaces for Mixed-Timing Systems with Application to Latency-Insensitive Protocols.
Proceedings of the 38th Design Automation Conference, 2001

2000
Low-Latency Asynchronous FIFO's Using Token Rings.
Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000), 2000


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