Steven M. Nowick

Affiliations:
  • Columbia University, New York City, USA


According to our database1, Steven M. Nowick authored at least 99 papers between 1989 and 2022.

Collaborative distances:

Awards

IEEE Fellow

IEEE Fellow 2009, "For contributions to asynchronous and mixed-timing integrated circuits and systems".

Timeline

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Bibliography

2022
An Asynchronous Soft Macro for Ultra-Low Power Communication in Neuromorphic Computing.
Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022

2021
Cost-Effective and Flexible Asynchronous Interconnect Technology for GALS Systems.
IEEE Micro, 2021

2019
A Continuous-Time Replication Strategy for Efficient Multicast in Asynchronous NoCs.
IEEE Trans. Very Large Scale Integr. Syst., 2019

Towards a Complete Methodology for Synthesizing Bundled-Data Asynchronous Circuits on FPGAs.
Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019

2017
Achieving Lightweight Multicast in Asynchronous NoCs Using a Continuous-Time Multi-Way Read Buffer.
Proceedings of the Eleventh IEEE/ACM International Symposium on Networks-on-Chip, 2017

Cost-Effective and Flexible Asynchronous Interconnect Technology for GALS Networks-on-Chip.
Proceedings of the New Generation of CAS, 2017

An asynchronous NoC router in a 14nm FinFET library: Comparison to an industrial synchronous counterpart.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Accurate Assessment of Bundled-Data Asynchronous NoCs Enabled by a Predictable and Efficient Hierarchical Synthesis Flow.
Proceedings of the 23rd IEEE International Symposium on Asynchronous Circuits and Systems, 2017

A High-Throughput Asynchronous Multi-resource Arbiter Using a Pipelined Assignment Approach.
Proceedings of the 23rd IEEE International Symposium on Asynchronous Circuits and Systems, 2017

2016
Achieving lightweight multicast in asynchronous networks-on-chip using local speculation.
Proceedings of the 53rd Annual Design Automation Conference, 2016

2015
Improving the Energy Efficiency of Pipelined Delay Lines Through Adaptive Granularity.
IEEE Trans. Very Large Scale Integr. Syst., 2015

Asynchronous Design - Part 2: Systems and Methodologies.
IEEE Des. Test, 2015

Asynchronous Design - Part 1: Overview and Recent Advances.
IEEE Des. Test, 2015

Increasing reconfigurability with memristive interconnects.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

A Lightweight Early Arbitration Method for Low-Latency Asynchronous 2D-Mesh NoC's.
Proceedings of the 52nd Annual Design Automation Conference, 2015

Increasing Impartiality and Robustness in High-Performance N-Way Asynchronous Arbiters.
Proceedings of the 21st IEEE International Symposium on Asynchronous Circuits and Systems, 2015

2014
A Flexible, Event-Driven Digital Filter With Frequency Response Independent of Input Sample Rate.
IEEE J. Solid State Circuits, 2014

Crossbar replication vs. sharing for virtual channel flow control in asynchronous NoCs: A comparative study.
Proceedings of the 22nd International Conference on Very Large Scale Integration, 2014

A low-latency asynchronous interconnection network with early arbitration resolution.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013
Robust and energy-efficient asynchronous dynamic pipelines for ultra-low-voltage operation using adaptive keeper control.
Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013

A flexible, clockless digital filter.
Proceedings of the ESSCIRC 2013, 2013

A transition-signaling bundled data NoC switch architecture for cost-effective GALS multicore systems.
Proceedings of the Design, Automation and Test in Europe, 2013

Soft MOUSETRAP: A Bundled-Data Asynchronous Pipeline Scheme Tolerant to Random Variations at Ultra-Low Supply Voltages.
Proceedings of the 19th IEEE International Symposium on Asynchronous Circuits and Systems, 2013

2012
Error-Correcting Unordered Codes and Hardware Support for Robust Asynchronous Global Communication.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

Designing pipelined delay lines with dynamically-adaptive granularity for low-energy applications.
Proceedings of the 30th International IEEE Conference on Computer Design, 2012

2011
A Low-Overhead Asynchronous Interconnection Network for GALS Chip Multiprocessors.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Introduction to Special Issue: Asynchrony in System Design.
ACM J. Emerg. Technol. Comput. Syst., 2011

High-Performance Asynchronous Pipelines: An Overview.
IEEE Des. Test Comput., 2011

A low-latency adaptive asynchronous interconnection network using bi-modal router nodes.
Proceedings of the NOCS 2011, 2011

A delay-insensitive bus-invert code and hardware support for robust asynchronous global communication.
Proceedings of the Design, Automation and Test in Europe, 2011

2010
An Adaptively Pipelined Mixed Synchronous-Asynchronous Digital FIR Filter Chip Operating at 1.3 Gigahertz.
IEEE Trans. Very Large Scale Integr. Syst., 2010

ACM Journal on Emerging Technologies in Computing Systems.
ACM Trans. Design Autom. Electr. Syst., 2010

Practical completion detection for 2-of-N delay-insensitive codes.
Proceedings of the 28th International Conference on Computer Design, 2010

An error-correcting unordered code and hardware support for robust asynchronous global communication.
Proceedings of the Design, Automation and Test in Europe, 2010

2009
Asynchronous Protocol Converters for Two-Phase Delay-Insensitive Global Communication.
IEEE Trans. Very Large Scale Integr. Syst., 2009

2008
Technology Mapping and Cell Merger for Asynchronous Threshold Networks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

A Level-Encoded Transition Signaling Protocol for High-Throughput Asynchronous Global Communication.
Proceedings of the 14th IEEE International Symposium on Asynchronous Circuits and Systems, 2008

Block-Level Relaxation for Timing-Robust Asynchronous Circuits Based on Eager Evaluation.
Proceedings of the 14th IEEE International Symposium on Asynchronous Circuits and Systems, 2008

2007
The Design of High-Performance Dynamic Asynchronous Pipelines: High-Capacity Style.
IEEE Trans. Very Large Scale Integr. Syst., 2007

The Design of High-Performance Dynamic Asynchronous Pipelines: Lookahead Style.
IEEE Trans. Very Large Scale Integr. Syst., 2007

MOUSETRAP: High-Speed Transition-Signaling Asynchronous Pipelines.
IEEE Trans. Very Large Scale Integr. Syst., 2007

An efficient algorithm for time separation of events in concurrent systems.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Efficient Asynchronous Protocol Converters for Two-Phase Delay-Insensitive Global Communication.
Proceedings of the 13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2007), 2007

A Cycle-Based Decomposition Method for Burst-Mode Asynchronous Controllers.
Proceedings of the 13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2007), 2007

Optimization of Robust Asynchronous Circuits by Local Input Completeness Relaxation.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006
Optimal Technology Mapping and Cell Merger for Asynchronous Threshold Networks.
Proceedings of the 12th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2006), 2006

2005
Test generation for ultra-high-speed asynchronous pipelines.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

A lattice-based framework for the classification and design of asynchronous pipelines.
Proceedings of the 42nd Design Automation Conference, 2005

Efficient performance analysis of asynchronous systems based on periodicity.
Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2005

2004
Robust interfaces for mixed-timing systems.
IEEE Trans. Very Large Scale Integr. Syst., 2004

High-throughput asynchronous datapath with software-controlled voltage scaling.
IEEE J. Solid State Circuits, 2004

Fast hazard detection in combinational circuits.
Proceedings of the 41th Design Automation Conference, 2004

2003
Guest Editorial.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

On the Existence of Hazard-Free Multi-Level Logic.
Proceedings of the 9th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2003), 2003

Asynchronous Datapath with Software-Controlled On-Chip Adaptive Voltage Scaling for Multirate Signal Processing Application.
Proceedings of the 9th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2003), 2003

2002
Resynthesis and Peephole Transformations for the Optimization of Large-Scale Asynchronous Systems.
Proceedings of the 11th IEEE/ACM International Workshop on Logic & Synthesis, 2002

High-Speed Non-Linear Asynchronous Pipelines.
Proceedings of the 2002 Design, 2002

A Burst-Mode Oriented Back-End for the Balsa Synthesis System.
Proceedings of the 2002 Design, 2002

2001
MOUSETRAP: Ultra-High-Speed Transition-Signaling Asynchronous Pipelines.
Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001

Transformations for the Synthesis and Optimization of Asynchronous Distributed Control.
Proceedings of the 38th Design Automation Conference, 2001

Robust Interfaces for Mixed-Timing Systems with Application to Latency-Insensitive Protocols.
Proceedings of the 38th Design Automation Conference, 2001

Sequential optimization of asynchronous and synchronous fintie-state machines.
Springer, ISBN: 978-0-7923-7425-1, 2001

2000
Synthesis for logical initializability of synchronous finite-state machines.
IEEE Trans. Very Large Scale Integr. Syst., 2000

High-Throughput Asynchronous Pipelines for Fine-Grain Dynamic Datapaths.
Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000), 2000

Low-Latency Asynchronous FIFO's Using Token Rings.
Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000), 2000

1999
Special Issue On Asynchronous Circuits And Systems.
Proc. IEEE, 1999

Modeling and design of asynchronous circuits.
Proc. IEEE, 1999

Applications of asynchronous circuits.
Proc. IEEE, 1999

OPTIMISTA: state minimization of asynchronous FSMs for optimum output logic.
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

Practical Advances in Asynchronous Design and in Asynchronous/Synchronous Interfaces.
Proceedings of the 36th Conference on Design Automation, 1999

1998
Architectural optimization for low-power nonpipelined asynchronous systems.
IEEE Trans. Very Large Scale Integr. Syst., 1998

Fast heuristic and exact algorithms for two-level hazard-free logic minimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

An Implicit Method for Hazard-Free Two-Level Logic Minimization.
Proceedings of the 4th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '98), 30 March, 1998

A Fast Asynchronous Huffman Decoder for Compressed-Code Embedded Processors.
Proceedings of the 4th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '98), 30 March, 1998

1997
Synthesis of asynchronous circuits for stuck-at and robust path delay fault testability.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997

Synthesis of low-power asynchronous circuits in a specified environment.
Proceedings of the 1997 International Symposium on Low Power Electronics and Design, 1997

Practical Advances in Asynchronous Design.
Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997

OPTIMIST: state minimization for optimal 2-level logic implementation.
Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

Speculative Completion for the Design of High-Performance Asynchronous Dynamic Adders.
Proceedings of the 3rd International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '97), 1997

A High-Speed Asynchronous Decompression Circuit for Embedded Processors.
Proceedings of the 17th Conference on Advanced Research in VLSI (ARVLSI '97), 1997

1996
Synthesis-for-Initializability of Asynchronous Sequential Machines.
Proceedings of the Proceedings IEEE International Test Conference 1996, 1996

Concurrency-oriented optimization for low-power asynchronous systems.
Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996

Espresso-HF: A Heuristic Hazard-Free Minimizer for Two-Level Logic.
Proceedings of the 33st Conference on Design Automation, 1996

Synthesis for Hazard-free Customized CMOS Complex-Gate Networks Under Multiple-Input Changes.
Proceedings of the 33st Conference on Design Automation, 1996

1995
Exact two-level minimization of hazard-free logic with multiple-input changes.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

Symbolic hazard-free minimization and encoding of asynchronous finite state machines.
Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

Estimation and bounding of energy consumption in burst-mode control circuits.
Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

Algorithms for the optimal state assignment of asynchronous state machines.
Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI '95), 1995

1994
A correctness criterion for asynchronous circuit validation and optimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994

UCLOCK: Automated Design of High-Peformance Unclocked State Machines.
Proceedings of the Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1994

1993
Automatic synthesis of burst-mode asynchronous controllers.
PhD thesis, 1993

The design of a high-performance cache controller: a case study in asynchronous synthesis.
Integr., 1993

1992
Specification and Automatic Verification of Self-Timed Queues.
Formal Methods Syst. Des., 1992

Synthesis of 3D Asynchronous State Machines.
Proceedings of the Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1992

Practical Asynchronous Controller Design.
Proceedings of the Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1992

1991
Synthesis of Asynchronous State Machines Using A Local Clock.
Proceedings of the Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1991

Automatic Synthesis of Locally-Clocked Asynchronous State Machines.
Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

1989
Automatic verification of speed-independent circuits with Petri net specifications.
Proceedings of the Computer Design: VLSI in Computers and Processors, 1989

Practicality of state-machine verification of speed-independent circuits.
Proceedings of the 1989 IEEE International Conference on Computer-Aided Design, 1989


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