Tiefu Li
Orcid: 0009-0007-5851-6519
According to our database1,
Tiefu Li authored at least 11 papers
between 2022 and 2026.
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Bibliography
2026
A Cryo-CMOS 4-5.9-GHz Fractional-N Cascaded PLL Achieving 36.9-fsrms Integrated Jitter and -69.1-dBc Fractional Spur.
IEEE Trans. Very Large Scale Integr. Syst., June, 2026
A Digital Baseband ASIC Targeting 99.999% Fidelity for Qubit Control and Readout with ROI-based Classification.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2026
A Fewer-Cycles, Resource-Efficient Concurrent Calibration Method for Compact Transmon Qubit Control and Readout Circuit.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2026
2024
IEEE Trans. Circuits Syst. II Express Briefs, September, 2024
IEEE Trans. Circuits Syst. II Express Briefs, March, 2024
29.4 A Cryo-CMOS Quantum Computing Unit Interface Chipset in 28nm Bulk CMOS with Phase-Detection Based Readout and Phase-Shifter Based Pulse Generation.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2023
A Polar-Modulation-Based Cryogenic Transmon Qubit State Controller in 28 nm Bulk CMOS for Superconducting Quantum Computing.
IEEE J. Solid State Circuits, November, 2023
Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
A 400uW 3.6GHz-4.6GHz Low Power Cryogenic CP-PLL with Transformer-Based VCO in 28nm Bulk CMOS.
Proceedings of the IEEE International Conference on Integrated Circuits, 2023
2022