Nele Mentens

According to our database1, Nele Mentens authored at least 107 papers between 2004 and 2022.

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Bibliography

2022
In-depth energy analysis of security algorithms and protocols for the Internet of Things.
J. Cryptogr. Eng., 2022

FOCUS: Frequency Based Detection of Covert Ultrasonic Signals.
Proceedings of the ICT Systems Security and Privacy Protection, 2022

Energy and side-channel security evaluation of near-threshold cryptographic circuits in 28nm FD-SOI technology.
Proceedings of the CF '22: 19th ACM International Conference on Computing Frontiers, Turin, Italy, May 17, 2022

2021
A Scalable SIMD RISC-V based Processor with Customized Vector Extensions for CRYSTALS-Kyber.
IACR Cryptol. ePrint Arch., 2021

Communication and Security Trade-Offs for Battery-Powered Devices: A Case Study on Wearable Medical Sensor Systems.
IEEE Access, 2021

Machine Learning for Misuse-Based Network Intrusion Detection: Overview, Unified Evaluation and Feature Choice Comparison Framework.
IEEE Access, 2021

Evaluating the ROCKY Countermeasure for Side-Channel Leakage.
Proceedings of the 29th IFIP/IEEE International Conference on Very Large Scale Integration, 2021

Low-Rate Overuse Flow Tracer (LOFT): An Efficient and Scalable Algorithm for Detecting Overuse Flows.
Proceedings of the 40th International Symposium on Reliable Distributed Systems, 2021

SoK - Network Intrusion Detection on FPGA.
Proceedings of the Security, Privacy, and Applied Cryptography Engineering, 2021

RESERVE: Remote Attestation of Intermittent IoT devices.
Proceedings of the SenSys '21: The 19th ACM Conference on Embedded Networked Sensor Systems, Coimbra, Portugal, November 15, 2021

ROCKY: Rotation Countermeasure for the Protection of Keys and Other Sensitive Data.
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2021

Speed Records in Network Flow Measurement on FPGA.
Proceedings of the 31st International Conference on Field-Programmable Logic and Applications, 2021

AITIA: Embedded AI Techniques for Industrial Applications.
Proceedings of the 31st International Conference on Field-Programmable Logic and Applications, 2021

Trusted Configuration in Cloud FPGAs.
Proceedings of the 29th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2021

Novel Non-cryptographic Hash Functions for Networking and Security Applications on FPGA.
Proceedings of the 24th Euromicro Conference on Digital System Design, 2021

Invited: Security Beyond Bulk Silicon: Opportunities and Challenges of Emerging Devices.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

Towards Real-Time Deep Learning-Based Network Intrusion Detection on FPGA.
Proceedings of the Applied Cryptography and Network Security Workshops, 2021

2020
Lightweight Ciphers and Their Side-Channel Resilience.
IEEE Trans. Computers, 2020

Side-channel countermeasures utilizing dynamic logic reconfiguration: Protecting AES/Rijndael and Serpent encryption in hardware.
Microprocess. Microsystems, 2020

PROOFS 2018 Editorial.
J. Cryptogr. Eng., 2020

On the feasibility of using evolvable hardware for hardware Trojan detection and prevention.
Appl. Soft Comput., 2020

SHeFU: Secure Hardware-Enabled Protocol for Firmware Updates.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Novel Bloom filter algorithms and architectures for ultra-high-speed network security applications.
Proceedings of the 23rd Euromicro Conference on Digital System Design, 2020

Breaking a fully Balanced ASIC Coprocessor Implementing Complete Addition Formulas on Weierstrass Elliptic Curves.
Proceedings of the 23rd Euromicro Conference on Digital System Design, 2020

INVITED: AI Utopia or Dystopia - On Securing AI Platforms.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

AITIA: Embedded AI Techniques for Embedded Industrial Applications.
Proceedings of the 2020 International Conference on Omni-layer Intelligent Systems, 2020

Evolvable Hardware Architectures on FPGA for Side-Channel Security.
Proceedings of the Applied Cryptography and Network Security Workshops, 2020

2019
Security on Plastics: Fake or Real?
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2019

Balancing elliptic curve coprocessors from bottom to top.
Microprocess. Microsystems, 2019

SHeLA: Scalable Heterogeneous Layered Attestation.
IEEE Internet Things J., 2019

A Novel FPGA Architecture and Protocol for the Self-attestation of Configurable Hardware.
IACR Cryptol. ePrint Arch., 2019

Efficient Utilization of DSPs and BRAMs Revisited: New AES-GCM Recipes on FPGAs.
IACR Cryptol. ePrint Arch., 2019

Communication and security trade-offs for wearable medical sensor systems in hospitals: work-in-progress.
Proceedings of the International Conference on Embedded Software Companion, 2019

Dynamic Logic Reconfiguration Based Side-Channel Protection of AES and Serpent.
Proceedings of the 22nd Euromicro Conference on Digital System Design, 2019

SACHa: Self-Attestation of Configurable Hardware.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

In Hardware We Trust: Gains and Pains of Hardware-assisted Security.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018
ES-TRNG: A High-throughput, Low-area True Random Number Generator based on Edge Sampling.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2018

High-speed Side-channel-protected Encryption and Authentication in Hardware.
IACR Cryptol. ePrint Arch., 2018

Rethinking Secure FPGAs: Towards a Cryptography-friendly Configurable Cell Architecture and its Automated Design Flow.
IACR Cryptol. ePrint Arch., 2018

Finding short and implementation-friendly addition chains with evolutionary algorithms.
J. Heuristics, 2018

A Systematic Performance Comparison of Ultra Low-Power AES S-Boxes.
Proceedings of the 28th International Symposium on Power and Timing Modeling, 2018

Combining analog and digital electronics in a hands-on introductory course.
Proceedings of the 12th European Workshop on Microelectronics Education, 2018

Design of a Fully Balanced ASIC Coprocessor Implementing Complete Addition Formulas on Weierstrass Elliptic Curves.
Proceedings of the 21st Euromicro Conference on Digital System Design, 2018

Storage and computation optimization of public-key schemes on embedded devices.
Proceedings of the 2018 4th International Conference on Cloud Computing Technologies and Applications, 2018

Digital signatures and signcryption schemes on embedded devices: a trade-off between computation and storage.
Proceedings of the 15th ACM International Conference on Computing Frontiers, 2018

200 Gbps Hardware Accelerated Encryption System for FPGA Network Cards.
Proceedings of the 2018 Workshop on Attacks and Solutions in Hardware Security, 2018

HeComm: End-to-end secured communication in a heterogeneous IoT environment via fog computing.
Proceedings of the 15th IEEE Annual Consumer Communications & Networking Conference, 2018

2017
Side-channel Analysis of Lightweight Ciphers: Does Lightweight Equal Easy?
IACR Cryptol. ePrint Arch., 2017

Hiding side-channel leakage through hardware randomization: A comprehensive overview.
Proceedings of the 2017 International Conference on Embedded Computer Systems: Architectures, 2017

Maximizing the throughput of threshold-protected AES-GCM implementations on FPGA.
Proceedings of the IEEE 2nd International Verification and Security Workshop, 2017

Side-channel analysis and machine learning: A practical perspective.
Proceedings of the 2017 International Joint Conference on Neural Networks, 2017

The Monte Carlo PUF.
Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

Area-optimized montgomery multiplication on IGLOO 2 FPGAs.
Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

Design of S-boxes Defined with Cellular Automata Rules.
Proceedings of the Computing Frontiers Conference, 2017

Do we need a holistic approach for the design of secure IoT systems?
Proceedings of the Computing Frontiers Conference, 2017

On-chip jitter measurement for true random number generators.
Proceedings of the 2017 Asian Hardware Oriented Security and Trust Symposium, 2017

2016
Guest Editorial.
IET Inf. Secur., 2016

Canary Numbers: Design for Light-weight Online Testability of True Random Number Generators.
IACR Cryptol. ePrint Arch., 2016

Low Power Montgomery Modular Multiplication on Reconfigurable Systems.
IACR Cryptol. ePrint Arch., 2016

A Search Strategy to Optimize the Affine Variant Properties of S-Boxes.
Proceedings of the Arithmetic of Finite Fields - 6th International Workshop, 2016

On the Construction of Hardware-Friendly 4\times 4 and 5\times 5 S-Boxes.
Proceedings of the Selected Areas in Cryptography - SAC 2016, 2016

Evolving Cryptographic Pseudorandom Number Generators.
Proceedings of the Parallel Problem Solving from Nature - PPSN XIV, 2016

Exploring the use of shift register lookup tables for Keccak implementations on Xilinx FPGAs.
Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

Evolutionary Algorithms for Finding Short Addition Chains: Going the Distance.
Proceedings of the Evolutionary Computation in Combinatorial Optimization, 2016

TOTAL: TRNG on-the-fly testing for attack detection using Lightweight hardware.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

PRNGs for Masking Applications and Their Mapping to Evolvable Hardware.
Proceedings of the Smart Card Research and Advanced Applications, 2016

Extreme Pipelining Towards the Best Area-Performance Trade-Off in Hardware.
Proceedings of the Progress in Cryptology - AFRICACRYPT 2016, 2016

A Fast and Compact FPGA Implementation of Elliptic Curve Cryptography Using Lambda Coordinates.
Proceedings of the Progress in Cryptology - AFRICACRYPT 2016, 2016

2015
Secure, Remote, Dynamic Reconfiguration of FPGAs.
ACM Trans. Reconfigurable Technol. Syst., 2015

Practical feasibility evaluation and improvement of a pay-per-use licensing scheme for hardware IP cores in Xilinx FPGAs.
J. Cryptogr. Eng., 2015

On-the-fly tests for non-ideal true random number generators.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Challenges in designing trustworthy cryptographic co-processors.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Embedded HW/SW platform for on-the-fly testing of true random number generators.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Study on impact of adding security in a 6LoWPAN based network.
Proceedings of the 2015 IEEE Conference on Communications and Network Security, 2015

DynamIA: Dynamic Hardware Reconfiguration in Industrial Applications.
Proceedings of the Applied Reconfigurable Computing - 11th International Symposium, 2015

2014
High-speed Polynomial Multiplication Architecture for Ring-LWE and SHE Cryptosystems.
IACR Cryptol. ePrint Arch., 2014

S-box pipelining using genetic algorithms for high-throughput AES implementations: How fast can we go?
IACR Cryptol. ePrint Arch., 2014

Compact Ring-LWE Cryptoprocessor.
Proceedings of the Cryptographic Hardware and Embedded Systems - CHES 2014, 2014

An Elliptic Curve Cryptographic Processor Using Edwards Curves and the Number Theoretic Transform.
Proceedings of the Cryptography and Information Security in the Balkans, 2014

2013
Compact Hardware Implementation of Ring-LWE Cryptosystems.
IACR Cryptol. ePrint Arch., 2013

Dietary Recommendations for Lightweight Block Ciphers: Power, Energy and Area Analysis of Recently Developed Architectures.
IACR Cryptol. ePrint Arch., 2013

A single-chip solution for the secure remote configuration of FPGAs using bitstream compression.
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2013

Remote FPGA design through eDiViDe - European Digital Virtual Design Lab.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

2012
Design space exploration for automatically generated cryptographic hardware using functional languages.
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

2011
Secure remote reconfiguration of an FPGA-based embedded system.
Proceedings of the 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2011

2010
Side-channel evaluation of FPGA implementations of binary Edwards curves.
Proceedings of the 17th IEEE International Conference on Electronics, 2010

Secure remote reconfiguration of FPGAs.
Proceedings of the Dynamically Reconfigurable Architectures, 11.07. - 16.07.2010, 2010

A compact FPGA-based architecture for elliptic curve cryptography over prime fields.
Proceedings of the 21st IEEE International Conference on Application-specific Systems Architectures and Processors, 2010

2009
Breaking ECC2K-130.
IACR Cryptol. ePrint Arch., 2009

The Certicom Challenges ECC2-X.
IACR Cryptol. ePrint Arch., 2009

Secure FPGA technologies and techniques.
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

2008
Power and Fault Analysis Resistance in Hardware through Dynamic Reconfiguration.
Proceedings of the Cryptographic Hardware and Embedded Systems, 2008

2007
A Side-channel Attack Resistant Programmable PKC Coprocessor for Embedded Applications.
Proceedings of the 2007 International Conference on Embedded Computer Systems: Architectures, 2007

Public-Key Cryptography for RFID-Tags.
Proceedings of the Fifth Annual IEEE International Conference on Pervasive Computing and Communications, 2007

Public-Key Cryptography on the Top of a Needle.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Efficient pipelining for modular multiplication architectures in prime fields.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

2006
An Elliptic Curve Processor Suitable For RFID-Tags.
IACR Cryptol. ePrint Arch., 2006

Flexible hardware architectures for curve-based cryptography.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Fpga-Oriented Secure Data Path Design: Implementation of a Public Key Coprocessor.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

Low-Cost Elliptic Curve Cryptography for Wireless Sensor Networks.
Proceedings of the Security and Privacy in Ad-Hoc and Sensor Networks, 2006

Reconfigurable Modular Arithmetic Logic Unit for High-Performance Public-Key Cryptosystems.
Proceedings of the Reconfigurable Computing: Architectures and Applications, 2006

Time-Memory Trade-Off Attack on FPGA Platforms: UNIX Password Cracking.
Proceedings of the Reconfigurable Computing: Architectures and Applications, 2006

2005
Side-Channel Issues for Designing Secure Hardware Implementations.
Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005

A Systematic Evaluation of Compact Hardware Implementations for the Rijndael S-Box.
Proceedings of the Topics in Cryptology, 2005

Side-channel aware design: Algorithms and Architectures for Elliptic Curve Cryptography over GF(2<sup>n</sup>).
Proceedings of the 16th IEEE International Conference on Application-Specific Systems, 2005

2004
An FPGA Implementation of a Montgomery Multiplier Over GF(2^m).
Comput. Artif. Intell., 2004

An FPGA implementation of an elliptic curve processor GF(2<sup>m</sup>).
Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004


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