Ting-Sheng Chao

According to our database¹, Ting-Sheng Chao authored at least 4 papers between 2009 and 2010.

Collaborative distances:

Dijkstra number² of six.
Erdős number³ of five.

Timeline

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In proceedings

Article

PhD thesis

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Bibliography

2010

A Pseudo Fractional-<i>N</i> Clock Generator with 50% Duty Cycle Output.

[BibT_eX]

[DOI]

Wei-Bin Yang

Yu-Lung Lo

Ting-Sheng Chao

IEICE Trans. Electron., 2010

2009

Designing an Ultralow-Voltage Phase-Locked Loop Using a Bulk-Driven Technique.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2009

High-Speed and Ultra-Low-Voltage Divide-by-4/5 Counter for Frequency Synthesizer.

[BibT_eX]

[DOI]

IEICE Trans. Electron., 2009

Designing ultra-low voltage PLL Using a bulk-driven technique.

[BibT_eX]

[DOI]

Proceedings of the 35th European Solid-State Circuits Conference, 2009

Ting-Sheng Chao

Timeline

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Links

On csauthors.net:

Bibliography

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