Tohru Adachi

According to our database1, Tohru Adachi authored at least 6 papers between 1982 and 2021.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2021
MN-Core - A Highly Efficient and Scalable Approach to Deep Learning.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021

1988
Software Environment for 500 MHz VLSI Test System "ULTIMATE".
Proceedings of the Proceedings International Test Conference 1988, 1988

1987
Top-Down Layout for Hierarchical Custom Design.
IEEE Des. Test, 1987

1986
An automatic cell pattern generation system for CMOS transistor-pair array LSI.
Integr., 1986

1985
An Integrated Design Automation System for VLSI Circuits.
IEEE Des. Test, 1985

1982
Hierarchical top-down layout design method for VLSI chip.
Proceedings of the 19th Design Automation Conference, 1982


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