Tsuneta Sudo

According to our database, Tsuneta Sudo authored at least 8 papers between 1981 and 1988.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

1988

Design automation systems in Japan.

Tsuneta Sudo

IEEE Des. Test, 1988

Key Technologies for 500 MHz VLSI Test System "ULTIMATE".

Teruo Tamama, Naoaki Narumi, Taiichi Otsuji, Masao Suzuki, Tsuneta Sudo

Proceedings of the Proceedings International Test Conference 1988, 1988

Packaging Technologies for the 500 MHz VLSI Test System "ULTIMATE".

Yoshimitsu Sakagawa, Yusio Akazawa, Naoaki Narumi, Akira Yoshii, Tsuneta Sudo

Proceedings of the Proceedings International Test Conference 1988, 1988

Software Environment for 500 MHz VLSI Test System "ULTIMATE".

Tohru Adachi, M. Tanno, Tsuneta Sudo

Proceedings of the Proceedings International Test Conference 1988, 1988

1985

Semiconductor Device Simulation at NTT.

Kiyoyuki Yokoyama, Masaaki Tomizawa, Akira Yoshii, Tsuneta Sudo

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1985

A large scale cellular array processor: AAP-1.

Toshio Kondo, Tayoshi Nakashima, Toshio Tsuchiya, Yoshi Sugiyama, Tsuneta Sudo

Proceedings of the 13th ACM Annual Conference on Computer Science, 1985

1982

Hierarchical top-down layout design method for VLSI chip.

Tohru Adachi, Hitoshi Kitazawa, Mitsuyoshi Nagatani, Tsuneta Sudo

Proceedings of the 19th Design Automation Conference, 1982

1981

Analysis and Definition of Overall Timing Accuracy in VLSI Test System.

Shigeru Sugamori, Kenji Yoshida, Hiromi Maruyama, Shinpei Kamata, Tsuneta Sudo

Proceedings of the Proceedings International Test Conference 1981, 1981