Tomas Nordström

According to our database1, Tomas Nordström authored at least 45 papers between 1990 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.



In proceedings 
PhD thesis 




A framework to generate domain-specific manycore architectures from dataflow programs.
Microprocess. Microsystems, 2020

Recurrent Neural Networks: An Embedded Computing Perspective.
IEEE Access, 2020

Using Harmonized Parabolic Synthesis to Implement a Single-Precision Floating-Point Square Root Unit.
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

On the Interference Management Between Non-Stationary Wireless Networks.
Proceedings of the 24th IEEE International Conference on Emerging Technologies and Factory Automation, 2019

Designing Domain-Specific Heterogeneous Architectures from Dataflow Programs.
Comput., 2018

Providing efficient support for real-time guarantees in a fibre-optic AWG-based network for embedded systems.
Opt. Switch. Netw., 2017

Efficient Single-Precision Floating-Point Division Using Harmonized Parabolic Synthesis.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

Towards Architectural Design Space Exploration for Heterogeneous Manycores.
Proceedings of the 24th Euromicro International Conference on Parallel, 2016

Dataflow Implementation of QR Decomposition on a Manycore.
Proceedings of the Fourth ACM International Workshop on Many-core Embedded Systems, 2016

The DEWI high-level architecture: Wireless sensor networks in industrial applications.
Proceedings of the Eleventh International Conference on Digital Information Management, 2016

On the Use of a Many-core Processor for Computational Fluid Dynamics Simulations.
Proceedings of the International Conference on Computational Science, 2015

Comparative simulation study of fast heuristics for power control in copper broadband networks.
Signal Process., 2014

An evaluation of code generation of dataflow languages on manycore architectures.
Proceedings of the 2014 IEEE 20th International Conference on Embedded and Real-Time Computing Systems and Applications, 2014

A running leap for embedded signal processing to future parallel platforms.
Proceedings of the WISE'14, 2014

Kickstarting high-performance energy-efficient manycore architectures with Epiphany.
Proceedings of the 48th Asilomar Conference on Signals, Systems and Computers, 2014

Low-complexity optimal discrete-rate spectrum balancing in digital subscriber lines.
Signal Process., 2013

Enabling greener DSL access networks by their stabilization with artificial noise and SNR margin.
Clust. Comput., 2013

Performance analysis of vectored wireline systems embracing channel uncertainty.
Proceedings of IEEE International Conference on Communications, 2013

Column Generation for Discrete-Rate Multi-User and Multi-Carrier Power Control.
IEEE Trans. Commun., 2012

Modeling and optimization of the line-driver power consumption in xDSL systems.
EURASIP J. Adv. Signal Process., 2012

Energy-saving by low-power modes in ADSL2.
Comput. Networks, 2012

Coverage Optimization in DSL Networks by Low-Complexity Discrete Spectrum Balancing.
Proceedings of the Global Communications Conference, 2011

Energy-Efficient DSL Using Vectoring.
Proceedings of the Global Communications Conference, 2011

Robust spectrum management for DMT-based systems.
IEEE Trans. Signal Process., 2010

Duality-Gap Bounds for Multi-Carrier Systems and Their Application to Periodic Scheduling.
Proceedings of IEEE International Conference on Communications, 2010

Energy efficient power back-off management for VDSL2 transmission.
Proceedings of the 17th European Signal Processing Conference, 2009

Performance Evaluation of the Cable Bundle Unique Power Back-Off Algorithm.
Proceedings of the AccessNets, Third International Conference on Access Networks, 2008

Verification of Multipair Copper-Cable Model by Measurements.
IEEE Trans. Instrum. Meas., 2007

Dynamic Spectrum Management for Standardized VDSL.
Proceedings of the IEEE International Conference on Acoustics, 2007

VDSL power back-off parameter optimization for a cable bundle.
Proceedings of the 15th European Signal Processing Conference, 2007

Spectrum balancing for DSL with restrictions on maximum transmit PSD.
Proceedings of the 2nd International ICST Conference on Access Networks, 2007

The Normalized-Rate Iterative Algorithm: A Practical Dynamic Spectrum Management Method for DSL.
EURASIP J. Adv. Signal Process., 2006

Advanced Signal Processing for Digital Subscriber Lines.
EURASIP J. Adv. Signal Process., 2006

Revised Upstream Power Back-Off For VDSL.
Proceedings of the 2006 IEEE International Conference on Acoustics Speech and Signal Processing, 2006

Adaptive subcarrier allocation, power control, and power allocation for multiuser FDD-DMT systems.
Proceedings of IEEE International Conference on Communications, 2004

Adaptive resource allocation in multiuser FDD-DMT systems.
Proceedings of the 2004 12th European Signal Processing Conference, 2004

Exploiting the common-mode signal in xDSL.
Proceedings of the 2004 12th European Signal Processing Conference, 2004

An approach to analog mitigation of RFI.
IEEE J. Sel. Areas Commun., 2002

On the capacity of the copper cable channel using the common mode.
Proceedings of the Global Telecommunications Conference, 2002

Splitting the recursive least-squares algorithm.
Proceedings of the Sixth International Symposium on Signal Processing and its Applications, 2001

An adaptive mixed-signal narrowband interference canceller for wireline transmission systems.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

A comparative study of speaker verification systems using the polycost database.
Proceedings of the 5th International Conference on Spoken Language Processing, Incorporating The 7th Australian International Speech Science and Technology Conference, Sydney Convention Centre, Sydney, Australia, 30th November, 1998

Using and Designing Massively Parallel Computers for Artificial Neural Neural Networks.
J. Parallel Distributed Comput., 1992

Using FPLs to Implement a Reconfigurable Highly Parallel Computer.
Proceedings of the Field-Programmable Gate Arrays: Architectures and Tools for Rapid Prototyping, Second International Workshop on Field-Programmable Logic and Applications, Vienna, Austria, August 31, 1992

Execution of neural network algorithms on an array of bit-serial processors.
Proceedings of the 10th IAPR International Conference on Pattern Recognition, 1990