Toshihiro Konishi

According to our database1, Toshihiro Konishi authored at least 18 papers between 2010 and 2015.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2015
Low-Jitter Design for Second-Order Time-to-Digital Converter Using Frequency Shift Oscillators.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015

An I/O-Sized ADC with Second-Order TDC and MOM Capacitor Voltage-to-Time Converter.
IEICE Trans. Electron., 2015

2014
A 2.23 ps RMS jitter 3 μs fast settling ADPLL using temperature compensation PLL controller.
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

An 8-bit I/O-sized ADC with second-order TDC and MOM capacitor voltage-to-time converter.
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

2013
A Second-Order All-Digital TDC with Low-Jitter Frequency Shift Oscillators and Dynamic Flipflops.
IEICE Trans. Electron., 2013

An Opampless Second-Order MASH ΔΣ ADC with Using Gated Ring Oscillator Time-to-Digital Converter.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013

A 38 μA wearable biosignal monitoring system with near field communication.
Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013

Temperature compensation using least mean squares for fast settling all-digital phase-locked loop.
Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013

A 14 µA ECG processor with robust heart rate monitor for a wearable healthcare system.
Proceedings of the ESSCIRC 2013, 2013

Noise-tolerant instantaneous heart rate and R-peak detection using short-term autocorrelation for wearable healthcare systems.
Proceedings of the 35th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2013

2012
A 61-dB SNDR 700 µm<sup>2</sup> second-order all-digital TDC with low-jitter frequency shift oscillators and dynamic flipflops.
Proceedings of the Symposium on VLSI Circuits, 2012

A 62-dB SNDR second-order gated ring oscillator TDC with two-stage dynamic D-type flipflops as a quantization noise propagator.
Proceedings of the 10th IEEE International NEWCAS Conference, 2012

A 51-dB SNDR DCO-based TDC using two-stage second-order noise shaping.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Instantaneous Heart Rate detection using short-time autocorrelation for wearable healthcare systems.
Proceedings of the Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2012

2011
A Low-Power Multi-Phase Oscillator with Transfer Gate Phase Coupler Enabling Even-Numbered Phase Output.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011

A Low-Power Multi Resolution Spectrum Sensing Architecture for a Wireless Sensor Network with Cognitive Radio.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011

A 40-nm 640-µm<sup>2</sup> 45-dB opampless all-digital second-order MASH ΔΣ ADC.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

2010
A 58-µW Single-Chip Sensor Node Processor with Communication Centric Design.
IEICE Trans. Electron., 2010


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