Masahiko Yoshimoto
According to our database1,
Masahiko Yoshimoto
authored at least 189 papers
between 1995 and 2020.
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Bibliography
2020
A 1.15-TOPS 6.57-TOPS/W Neural Network Processor for Multi-Scale Object Detection With Reduced Convolutional Operations.
IEEE J. Sel. Top. Signal Process., 2020
Heartbeat Interval Error Compensation Method for Low Sampling Rates Photoplethysmography Sensors.
IEICE Trans. Commun., 2020
Proceedings of the 2nd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2020
Proceedings of the 2nd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2020
2019
Multimodal Cardiovascular Information Monitor Using Piezoelectric Transducers for Wearable Healthcare.
J. Signal Process. Syst., 2019
Energy-Efficient Spectral Analysis Method Using Autoregressive Model-Based Approach for Internet of Things.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
A 28-nm FD-SOI 8T Dual-Port SRAM for Low-Energy Image Processor With Selective Sourceline Drive Scheme.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
Low-Noise Photoplethysmography Sensor Using Correlated Double Sampling for Heartbeat Interval Acquisition.
IEEE Trans. Biomed. Circuits Syst., 2019
Recent Progress of Biomedical Processor SoC for Wearable Healthcare Application: A Review.
IEICE Trans. Electron., 2019
Non-Contact Instantaneous Heart Rate Extraction System Using 24-GHz Microwave Doppler Sensor.
IEICE Trans. Commun., 2019
A Low-Power Photoplethysmography Sensor using Correlated Double Sampling and Reference Readout Circuit.
Proceedings of the 2019 IEEE SENSORS, Montreal, QC, Canada, October 27-30, 2019, 2019
A Heartbeat Interval Error Compensation Method Using Multiple Linear Regression for Photoplethysmography Sensors.
Proceedings of the 2019 IEEE Biomedical Circuits and Systems Conference, 2019
An IoT Sensor Node SoC with Dynamic Power Scheduling for Sustainable Operation in Energy Harvesting Environment.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019
2018
IEICE Trans. Electron., 2018
A low power, VLSI object recognition processor using Sparse FIND feature for 60 fps HDTV resolution video [IEICE Electronics Express Vol. 14(2017) No. 15 pp. 20170668].
IEICE Electron. Express, 2018
Adaptive Learning Rate Adjustment with Short-Term Pre-Training in Data-Parallel Deep Learning.
Proceedings of the 2018 IEEE International Workshop on Signal Processing Systems, 2018
Hardware Implementation of Autoregressive Model Estimation Using Burg's Method for Low-Energy Spectral Analysis.
Proceedings of the 2018 IEEE International Workshop on Signal Processing Systems, 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
28-nm FD-SOI Dual-Port SRAM with MSB-Based Inversion Logic for Low-Power Deep Learning.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018
Layer Skip Learning using LARS variables for 39% Faster Conversion Time and Lower Bandwidth.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018
Proceedings of the 2018 IEEE Global Conference on Signal and Information Processing, 2018
2017
A low power, VLSI object recognition processor using Sparse FIND feature for 60 fps HDTV resolution video.
IEICE Electron. Express, 2017
FPGA implementation of object recognition processor for HDTV resolution video using sparse FIND feature.
Proceedings of the 2017 IEEE International Workshop on Signal Processing Systems, 2017
A layer-block-wise pipeline for memory and bandwidth reduction in distributed deep learning.
Proceedings of the 27th IEEE International Workshop on Machine Learning for Signal Processing, 2017
A swallowable sensing device platform with wireless power feeding and chemical reaction actuator.
Proceedings of the 2017 39th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC), 2017
Non-contact biometric identification and authentication using microwave Doppler sensor.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2017
Capacitively coupled ECG sensor system with digitally assisted noise cancellation for wearable application.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2017
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2017
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017
2016
A Counter-based Read Circuit Tolerant to Process Variation for 0.4-V Operating STT-MRAM.
IPSJ Trans. Syst. LSI Des. Methodol., 2016
A 28-nm 484-fJ/writecycle 650-fJ/readcycle 8T Three-Port FD-SOI SRAM for Image Processor.
IEICE Trans. Electron., 2016
Error Propagation Analysis for Single Event Upset considering Masking Effects on Re-Convergent Path.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016
An soft error propagation analysis considering logical masking effect on re-convergent path.
Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design, 2016
A 15-μA metabolic equivalents monitoring system using adaptive acceleration sampling and normally off computing.
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016
An low-energy 8T dual-port SRAM for image processor with selective sourceline drive scheme in 28-nm FD-SOI process technology.
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016
Low-power metabolic equivalents estimation algorithm using adaptive acceleration sampling.
Proceedings of the 38th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2016
Proceedings of the 38th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2016
Adaptive noise cancellation method for capacitively coupled ECG sensor using single insulated electrode.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2016
Non-contact Instantaneous Heart Rate Monitoring Using Microwave Doppler Sensor and Time-Frequency Domain Analysis.
Proceedings of the 16th IEEE International Conference on Bioinformatics and Bioengineering, 2016
Capacitively coupled ECG sensor using a single electrode with adaptive power-line noise cancellation.
Proceedings of the 2016 IEEE-EMBS International Conference on Biomedical and Health Informatics, 2016
2015
IEEE Trans. Biomed. Circuits Syst., 2015
IEEE Trans. Biomed. Circuits Syst., 2015
Low-Jitter Design for Second-Order Time-to-Digital Converter Using Frequency Shift Oscillators.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015
IEICE Trans. Electron., 2015
A Fast Settling All Digital PLL Using Temperature Compensated Oscillator Tuning Word Estimation Algorithm.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015
IEICE Trans. Electron., 2015
Noise Tolerant Heart Rate Extraction Algorithm Using Short-Term Autocorrelation for Wearable Healthcare Systems.
IEICE Trans. Inf. Syst., 2015
Proceedings of the 15th Non-Volatile Memory Technology Symposium, 2015
A low power 6T-4C non-volatile memory using charge sharing and non-precharge techniques.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
An accurate soft error propagation analysis technique considering temporal masking disablement.
Proceedings of the 21st IEEE International On-Line Testing Symposium, 2015
A more acceptable endoluminal implantation for remotely monitoring ingestible sensors anchored to the stomach wall.
Proceedings of the 37th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2015
Physical activity group classification algorithm using triaxial acceleration and heart rate.
Proceedings of the 37th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2015
Non-contact and noise tolerant heart rate monitoring using microwave doppler sensor and range imagery.
Proceedings of the 37th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2015
Large displacement haptic stimulus actuator using piezoelectric pump for wearable devices.
Proceedings of the 37th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2015
A 298-fJ/writecycle 650-fJ/readcycle 8T three-port SRAM in 28-nm FD-SOI process technology for image processor.
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015
Analysis of Soft Error Propagation Considering Masking Effects on Re-Convergent Path.
Proceedings of the 24th IEEE Asian Test Symposium, 2015
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015
A 14µA ECG processor with noise tolerant heart rate extractor and FeRAM for wearable healthcare systems.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015
2014
J. Signal Process. Syst., 2014
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014
A 40-nm Resilient Cache Memory for Dynamic Variation Tolerance Delivering ×91 Failure Rate Improvement under 35% Supply Voltage Fluctuation.
IEICE Trans. Electron., 2014
IEICE Electron. Express, 2014
A 40-nm resilient cache memory for dynamic variation tolerance with bit-enhancing memory and on-chip diagnosis structures delivering ×91 failure rate improvement.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
A 2.23 ps RMS jitter 3 μs fast settling ADPLL using temperature compensation PLL controller.
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014
An 8-bit I/O-sized ADC with second-order TDC and MOM capacitor voltage-to-time converter.
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014
Noise tolerant QRS detection using template matching with short-term autocorrelation.
Proceedings of the 36th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2014
A 6.14µA normally-off ECG-SoC with noise tolerant heart rate extractor for wearable healthcare systems.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2014
A 2.4 pJ ferroelectric-based non-volatile flip-flop with 10-year data retention capability.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014
A Low-Latency DMR Architecture with Efficient Recovering Scheme Exploiting Simultaneously Copiable SRAM.
Proceedings of the ARCS 2014, 2014
2013
IPSJ Trans. Syst. LSI Des. Methodol., 2013
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013
A Sub-100 mW Dual-Core HOG Accelerator VLSI for Parallel Feature Extraction Processing for HDTV Resolution Video.
IEICE Trans. Electron., 2013
A Second-Order All-Digital TDC with Low-Jitter Frequency Shift Oscillators and Dynamic Flipflops.
IEICE Trans. Electron., 2013
An Opampless Second-Order MASH ΔΣ ADC with Using Gated Ring Oscillator Time-to-Digital Converter.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013
Reconfiguring Cache Associativity: Adaptive Cache Design for Wide-Range Reliable Low-Voltage Operation Using 7T/14T SRAM.
IEICE Trans. Electron., 2013
IEICE Trans. Electron., 2013
A 40-NM 54-MW 3×-real-time VLSI processor for 60-kWord continuous speech recognition.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2013
Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013
Temperature compensation using least mean squares for fast settling all-digital phase-locked loop.
Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013
Energy-efficient Spin-Transfer Torque RAM cache exploiting additional all-zero-data flags.
Proceedings of the International Symposium on Quality Electronic Design, 2013
A sub-100-milliwatt dual-core HOG accelerator VLSI for real-time multiple object detection.
Proceedings of the IEEE International Conference on Acoustics, 2013
A 14 µA ECG processor with robust heart rate monitor for a wearable healthcare system.
Proceedings of the ESSCIRC 2013, 2013
Noise-tolerant instantaneous heart rate and R-peak detection using short-term autocorrelation for wearable healthcare systems.
Proceedings of the 35th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2013
A 40-nm 8T SRAM with selective source line control of read bitlines and address preset structure.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013
Low-power hardware implementation of noise tolerant heart rate extractor for a wearable monitoring system.
Proceedings of the 13th IEEE International Conference on BioInformatics and BioEngineering, 2013
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013
A physical unclonable function chip exploiting load transistors' variation in SRAM bitcells.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013
2012
IEEE Trans. Circuits Syst. I Regul. Pap., 2012
0.5-V 4-MB Variation-Aware Cache Architecture Using 7T/14T SRAM and Its Testing Scheme.
IPSJ Trans. Syst. LSI Des. Methodol., 2012
IEICE Trans. Electron., 2012
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012
Multiple-Bit-Upset and Single-Bit-Upset Resilient 8T SRAM Bitcell Layout with Divided Wordline Structure.
IEICE Trans. Electron., 2012
A 128-bit Chip Identification Generating Scheme Exploiting Load Transistors' Variation in SRAM Bitcells.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012
A 0.15-µm FD-SOI Substrate Bias Control SRAM with Inter-Die Variability Compensation Scheme.
IEICE Trans. Electron., 2012
A Process-Variation-Adaptive Network-on-Chip with Variable-Cycle Routers and Variable-Cycle Pipeline Adaptive Routing.
IEICE Trans. Electron., 2012
IEICE Trans. Commun., 2012
IEICE Electron. Express, 2012
IEICE Electron. Express, 2012
A 61-dB SNDR 700 µm<sup>2</sup> second-order all-digital TDC with low-jitter frequency shift oscillators and dynamic flipflops.
Proceedings of the Symposium on VLSI Circuits, 2012
Architectural Study of HOG Feature Extraction Processor for Real-Time Object Detection.
Proceedings of the 2012 IEEE Workshop on Signal Processing Systems, 2012
A 62-dB SNDR second-order gated ring oscillator TDC with two-stage dynamic D-type flipflops as a quantization noise propagator.
Proceedings of the 10th IEEE International NEWCAS Conference, 2012
A 40-nm 256-Kb 0.6-V operation half-select resilient 8T SRAM with sequential writing technique enabling 367-mV VDDmin reduction.
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012
A 40-nm 256-Kb Sub-10 pJ/Access 8t SRAM with read bitline amplitude limiting (RBAL) scheme.
Proceedings of the International Symposium on Low Power Electronics and Design, 2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
Proceedings of the 18th IEEE International On-Line Testing Symposium, 2012
Proceedings of the Third International Conference on Networking and Computing, 2012
Instantaneous Heart Rate detection using short-time autocorrelation for wearable healthcare systems.
Proceedings of the Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2012
A 40-nm 168-mW 2.4×-real-time VLSI processor for 60-kWord continuous speech recognition.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012
Proceedings of the ARCS 2012 Workshops, 28. Februar - 2. März 2012, München, Germany, 2012
Proceedings of the 19th Asia-Pacific Software Engineering Conference, 2012
2011
J. Inf. Process., 2011
IPSJ Trans. Syst. LSI Des. Methodol., 2011
7T SRAM Enabling Low-Energy Instantaneous Block Copy and Its Application to Transactional Memory.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011
VLSI Architecture of GMM Processing and Viterbi Decoder for 60, 000-Word Real-Time Continuous Speech Recognition.
IEICE Trans. Electron., 2011
A Low-Power Real-Time SIFT Descriptor Generation Engine for Full-HDTV Video Recognition.
IEICE Trans. Electron., 2011
A Low-Power Multi-Phase Oscillator with Transfer Gate Phase Coupler Enabling Even-Numbered Phase Output.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011
A Low-Power Multi Resolution Spectrum Sensing Architecture for a Wireless Sensor Network with Cognitive Radio.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011
Block-basis on-line BIST architecture for embedded SRAM using wordline and bitcell voltage optimal control.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
Multiple-bit-upset and single-bit-upset resilient 8T SRAM bitcell layout with divided wordline structure.
Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011
256-KB associativity-reconfigurable cache with 7T/14T SRAM for aggressive DVS down to 0.57 V.
Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011
Data Aggregation Protocol for Multiple Sound Sources Acquisition with Microphone Array Network.
Proceedings of 20th International Conference on Computer Communications and Networks, 2011
A 128-bit chip identification generating scheme exploiting SRAM bitcells with failure rate of 4.45 × 10<sup>-19</sup>.
Proceedings of the 37th European Solid-State Circuits Conference, 2011
Model-based fault injection for failure effect analysis - Evaluation of dependable SRAM for vehicle control units.
Proceedings of the IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W 2011), 2011
Proceedings of the 14th Euromicro Conference on Digital System Design, 2011
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011
2010
IEICE Trans. Electron., 2010
A power-variation model for sensor node and the impact against life time of wireless sensor networks.
IEICE Electron. Express, 2010
0.5-V operation variation-aware word-enhancing cache architecture using 7T/14T hybrid SRAM.
Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Fast and Low-Memory-Bandwidth Architecture of SIFT Descriptor Generation with Scalability on Speed and Accuracy for VGA Video.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2010
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010
2009
A 433-MHz Rail-to-Rail Voltage Amplifier with Carrier Sensing Function for Wireless Sensor Networks.
IEICE Trans. Electron., 2009
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009
An ultra-low-power VAD hardware implementation for intelligent ubiquitous sensor networks.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2009
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009
Parallelized viterbi processor for 5, 000-word large-vocabulary real-time continuous speech recognition FPGA system.
Proceedings of the INTERSPEECH 2009, 2009
2008
Novel Video Memory Reduces 45% of Bitline Power Using Majority Logic and Data-Bit Reordering.
IEEE Trans. Very Large Scale Integr. Syst., 2008
IEICE Trans. Commun., 2008
IEICE Trans. Electron., 2008
A Sub 100 mW H.264 MP@L4.1 Integer-Pel Motion Estimation Processor Core for MBAFF Encoding with Reconfigurable Ring-Connected Systolic Array and Segmentation-Free, Rectangle-Access Search-Window Buffer.
IEICE Trans. Electron., 2008
IEICE Trans. Electron., 2008
Counter-Based Broadcasting with Hop Count Aware Random Assessment Delay Extension for Wireless Sensor Networks.
IEICE Trans. Commun., 2008
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008
A sub 100 mW H.264/AVC MP@L4.1 integer-pel motion estimation processor VLSI for MBAFF encoding.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
An H.264/AVC MP@L4.1 quarter-pel motion estimation processor VLSI for real-time MBAFF encoding.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008
A low memory bandwidth Gaussian mixture model (GMM) processor for 20, 000-word real-time speech recognition FPGA system.
Proceedings of the 2008 International Conference on Field-Programmable Technology, 2008
2007
Area Optimization in 6T and 8T SRAM Cells Considering <i>V</i><sub>th</sub> Variation in Future Processes.
IEICE Trans. Electron., 2007
Area Comparison between 6T and 8T SRAM Cells in Dual-<i>V</i><sub>dd</sub> Scheme and DVS Scheme.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007
Data Transmission Scheduling Based on RTS/CTS Exchange for Periodic Data Gathering Sensor Networks.
IEICE Trans. Commun., 2007
Service Interval Optimization with Delay Bound Guarantee for HCCA in IEEE 802.11e WLANs.
IEICE Trans. Commun., 2007
Proceedings of the IEEE Wireless Communications and Networking Conference, 2007
Multipath Routing using Isochronous Medium Access Control with Multi Wakeup Period for Wireless Sensor Networks.
Proceedings of the 4th IEEE International Symposium on Wireless Communication Systems, 2007
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007
Power and Memory Bandwidth Reduction of an H.264/AVC HDTV Decoder LSI with Elastic Pipeline Architecture.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007
2006
A 0.3-V Operating, <i>V</i><sub>th</sub>-Variation-Tolerant SRAM under DVS Environment for Memory-Rich SoC in 90-nm Technology Era and Beyond.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006
A Sub-mW H.264 Baseline-Profile Motion Estimation Processor Core with a VLSI-Oriented Block Partitioning Strategy and SIMD/Systolic-Array Architecture.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006
A Power- and Area-Efficient SRAM Core Architecture with Segmentation-Free and Horizontal/Vertical Accessibility for Super-Parallel Video Processing.
IEICE Trans. Electron., 2006
VLSI Architecture Study of a Real-Time Scalable Optical Flow Processor for Video Segmentation.
IEICE Trans. Electron., 2006
Aggregation Efficiency-Aware Greedy Incremental Tree Routing for Wireless Sensor Networks.
IEICE Trans. Commun., 2006
A 50% Power Reduction in H.264/AVC HDTV Video Decoder LSI by Dynamic Voltage Scaling in Elastic Pipeline.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006
A Feed-Forward Dynamic VDD-VBB-Frequency Management for Low Power Motion Video Compression on 90NM Risc Processor.
Intell. Autom. Soft Comput., 2006
A Power- and Area-Efficient SRAM Core Architecture for Super-Parallel Video Processing.
Proceedings of the IFIP VLSI-SoC 2006, 2006
A two-port SRAM for real-time video processor saving 53% of bitline power with majority logic and data-bit reordering.
Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006
Proceedings of the 2006 International Conference on Parallel Processing Workshops (ICPP Workshops 2006), 2006
2005
A 95 mW MPEG2 MP@HL Motion Estimation Processor Core for Portable High-Resolution Video Application.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005
IEICE Trans. Electron., 2005
Power-Minimum Frequency/Voltage Cooperative Management Method for VLSI Processor in Leakage-Dominant Technology Era.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005
2004
IEEE J. Solid State Circuits, 2004
2003
Int. J. Mob. Commun., 2003
The development and impact on business of the world's first live video streaming distribution platform for 3G mobile videophone terminals.
Int. J. Electron. Bus., 2003
Proceedings of the IEEE Custom Integrated Circuits Conference, 2003
2002
An ultra low power, realtime MPEG2 MP@HL motion estimation processor core with SIMD datapath architecture optimized for gradient descent search algorithm.
Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, 2002
2001
Proceedings of the 2001 International Conference on Image Processing, 2001
2000
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
Media processor core architecture for realtime, bi-directional MPEG4/H.26X codec with 30 fr/s for CIF-video.
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, 2000
1995
A half-pel precision MPEG2 motion-estimation processor with concurrent three-vector search.
IEEE J. Solid State Circuits, December, 1995
Proceedings of the 1995 International Conference on Acoustics, 1995