Toshihiro Minami

According to our database, Toshihiro Minami authored at least 10 papers between 1991 and 2007.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2007

Single-Chip MPEG-2 422P@HL CODEC LSI With Multichip Configuration for Large Scale Processing Beyond HDTV Level.

Hiroe Iwasaki, Jiro Naganuma, Koyo Nitta, Ken Nakamura, Takeshi Yoshitome, Mitsuo Ogura, Yasuyuki Nakajima, Yutaka Tashiro, Takayuki Onishi, Mitsuo Ikeda, Toshihiro Minami, Makoto Endo, Yoshiyuki Yashima

IEEE Trans. Very Large Scale Integr. Syst., 2007

1999

A 4: 2: 2P@ML MPEG-2 video encoder board using an enhanced MP@ML video encoder LSI.

Takeshi Yoshitome, Toshihiro Minami, Mitsuo Ikeda, Koyo Nitta, Kazuhito Suguri

IEEE Trans. Consumer Electron., 1999

SuperENC: MPEG-2 video encoder chip.

Mitsuo Ikeda, Toshio Kondo, Koyo Nitta, Kazuhito Suguri, Takeshi Yoshitome, Toshihiro Minami, Hiroe Iwasaki, Katsuyuki Ochiai, Jiro Naganuma, Makoto Endo, Yutaka Tashiro, Hiroshi Watanabe, Naoki Kobayashi, Tsuneo Okubo, Ryota Kasai

IEEE Micro, 1999

An MPEG-2 Video Encoder LSI with Scalability for HDTV based on Three-layer Cooperative Architecture.

Mitsuo Ikeda, Toshio Kondo, Koyo Nitta, Kazuhito Suguri, Takeshi Yoshitome, Toshihiro Minami, Jiro Naganuma, Takeshi Ogura

Proceedings of the 1999 Design, 1999

1996

Two-chip MPEG-2 video encoder.

Toshio Kondo, Kazuhito Suguri, Mitsuo Ikeda, Tetsuya Abe, Hiroaki Matsuda, Tsuneo Okubo, Kenji Ogura, Yutaka Tashiro, Naoki Ono, Toshihiro Minami, Ritsu Kusaba, Takeshi Ikenaga, Nobutaro Shibata, Ryota Kasai, Koji Otsu, Fumiaki Nakagawa, Yasuhiko Sato

IEEE Micro, 1996

A real-time motion estimation and compensation LSI with wide search range for MPEG2 video encoding.

Kazuhito Suguri, Toshihiro Minami, Hiroaki Matsuda, Ritsu Kusaba, Toshio Kondo, Ryota Kasai, Takumi Watanabe, Hidenuri Sato, Nobutarou Shibata, Yutaka Tashiro, Takaaki Izuoka, Atsushi Shimizu, Hiroshi Kotera

IEEE J. Solid State Circuits, 1996

1992

Architecture and implementation of a highly parallel single-chip video DSP.

Hironori Yamauchi, Yutaka Tashiro, Toshihiro Minami, Yutaka Suzuki

IEEE Trans. Circuits Syst. Video Technol., 1992

1991

A 300-MPOS video signal processor with a parallel architecture.

Toshihiro Minami, Ryota Kasai, Hironori Yamauchi, Yutaka Tashiro, Jun-ichi Takahashi, Shigeru Date

IEEE J. Solid State Circuits, December, 1991

An Organized Firmware Verification Environment for the Programmable Image DSP.

Yutaka Tashiro, Hironori Yamauchi, Toshihiro Minami, Tetsuo Tajiri, Yutaka Suzuki

Proceedings of the Proceedings IEEE International Test Conference 1991, 1991

A highly-parallel single-chip DSP architecture for video signal processing.

Hironori Yamauchi, Yutaka Tashiro, Toshihiro Minami, Yutaka Suzuki

Proceedings of the 1991 International Conference on Acoustics, 1991