Hironori Yamauchi

According to our database, Hironori Yamauchi authored at least 21 papers between 1985 and 2019.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2019

Improved face image super-resolution with restricted patch-searching area.

Suhail Hamdan, Yohei Fukumizu, Tomonori Izumi, Hironori Yamauchi

Proceedings of the 3rd International Conference on Cryptography, Security and Privacy, 2019

2012

Robustly separating sound components in human body based on 2-ch ICA and EM algorithm with dirichlet distribution.

Kenji Hashiodani, S. Takada, Yohei Fukumizu, Hironori Yamauchi, Yoshimasa Kurumi, Tohru Tani

Proceedings of 2012 IEEE-EMBS International Conference on Biomedical and Health Informatics, 2012

2010

Signal and noise separation in medical diagnostic system based on independent component analysis.

Abdullah K. Khan, Tatsuya Onoue, Kenji Hashiodani, Yohei Fukumizu, Hironori Yamauchi

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

2009

A Gabor Pseudo Fisherface Based Face Recognition Algorithm for LSI Implementation.

Yohei Fukumizu, Tomoaki Takano, Yasuyuki Oshima, Toshihiko Terada, Hironori Yamauchi

Proceedings of the Fifth International Conference on Intelligent Information Hiding and Multimedia Signal Processing (IIH-MSP 2009), 2009

2008

Hybrid Architecture of Genetic Algorithm and Simulated Annealing.

Masaya Yoshikawa, Hironori Yamauchi, Hidekazu Terai

Eng. Lett., 2008

A CDFG generating method from C program for LSI design.

Toshiyuki Kato, Takaaki Miyauchi, Yoshizo Osumi, Hironori Yamauchi, Hideto Nishikado, Takaaki Miyake, Shiro Kobayashi

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

2006

Human Behavior Recognition for Daily Task Assistance using Sparse Range Data Observations.

Akira Utsumi, Hirotake Yamazoe, Shinji Abe, Daisuke Kanbara, Hironori Yamauchi

Proceedings of the Ninth International Conference on Control, 2006

Configurable multi-processor architecture and its processor element design.

Tsutomu Nishimura, Takuji Miki, Hiroaki Sugiura, Yuki Matsumoto, Masatsugu Kobayashi, Toshiyuki Kato, Tsutomu Eda, Hironori Yamauchi

Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005

DWT Based Robust Watermarking Embed Using CRC-32 Techniques.

Sadi Vural, Hiromi Tomii, Hironori Yamauchi

Proceedings of the Third World Enformatika Conference, 2005

Traceable robust watermarking for digital cinema system.

Sadi Vural, Hiromi Tomii, Hironori Yamauchi

Proceedings of the Eighth International Symposium on Signal Processing and Its Applications, 2005

Video watermarking for digital cinema contents.

Sadi Vural, Hiromi Tomii, Hironori Yamauchi

Proceedings of the 13th European Signal Processing Conference, 2005

2004

VLSI processor architecture for real-time GA processing and PE-VLSI design.

Tetsuya Imai, Masaya Yoshikawa, Hidekazu Terai, Hironori Yamauchi

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2002

Blurred Image Restoration by Using Real-Coded Genetic Algorithm.

Hideto Nishikado, Hiroyuki Murata, Motonori Yamaji, Hironori Yamauchi

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002

Scalable GA processor architecture and its implementation of processor-element.

Tetsuya Imai, Masaya Yoshikawa, Hidekazu Terai, Hironori Yamauchi

Proceedings of the IEEE International Conference on Acoustics, 2002

1997

Guest Editors' Introduction.

Keshab K. Parhi, Takao Nishitani, Hironori Yamauchi

J. VLSI Signal Process., 1997

1992

Architecture and implementation of a highly parallel single-chip video DSP.

Hironori Yamauchi, Yutaka Tashiro, Toshihiro Minami, Yutaka Suzuki

IEEE Trans. Circuits Syst. Video Technol., 1992

1991

An Organized Firmware Verification Environment for the Programmable Image DSP.

Yutaka Tashiro, Hironori Yamauchi, Toshihiro Minami, Tetsuo Tajiri, Yutaka Suzuki

Proceedings of the Proceedings IEEE International Test Conference 1991, 1991

A highly-parallel single-chip DSP architecture for video signal processing.

Hironori Yamauchi, Yutaka Tashiro, Toshihiro Minami, Yutaka Suzuki

Proceedings of the 1991 International Conference on Acoustics, 1991

A real-time 256×256 point two-dimensional FFT single-chip processor.

Hiroshi Miyanaga, Hironori Yamauchi, Kazuhiro Matsuda

Proceedings of the 1991 International Conference on Acoustics, 1991

1986

A 50ns floating-point signal processor VLSI.

Takao Kaneko, Hironori Yamauchi, Atsushi Iwata

Proceedings of the IEEE International Conference on Acoustics, 1986

1985

An 18-bit floating-point signal processor VLSI with an on-chip 512W dual-port RAM.

Hironori Yamauchi, Takao Kaneko, Tsutomu Kobayashi, Atsushi Iwata, Sadayasu Ono

Proceedings of the IEEE International Conference on Acoustics, 1985