Jürgen Teich

According to our database1, Jürgen Teich authored at least 534 papers between 1991 and 2019.

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Bibliography

2019
Automatic Optimization of the VLAN Partitioning in Automotive Communication Networks.
ACM Trans. Design Autom. Electr. Syst., 2019

Compilation of Dataflow Applications for Multi-Cores using Adaptive Multi-Objective Optimization.
ACM Trans. Design Autom. Electr. Syst., 2019

Efficient Mapping of Streaming Applications for Image Processing on Graphics Cards.
T. HiPEAC, 2019

Hard real-time application mapping reconfiguration for NoC-based many-core systems.
Real-Time Systems, 2019

Conference Reports: Recap of DATE 2019 in Florence, Italy.
IEEE Design & Test, 2019

Variety-aware Routing Encoding for Efficient Design Space Exploration of Automotive Communication Networks.
Proceedings of the 5th International Conference on Vehicle Technology and Intelligent Transport Systems, 2019

On the Analytic Evaluation of Schedules via Max-Plus Algebra for DSE of Multi-Core Architectures.
Proceedings of the 22nd International Workshop on Software and Compilers for Embedded Systems, 2019

SYCL Code Generation for Multigrid Methods.
Proceedings of the 22nd International Workshop on Software and Compilers for Embedded Systems, 2019

Optimizing Exploratory Workflows for Embedded Platform Trace Analysis and Its Application to Mobile Devices.
Proceedings of the HCI International 2019 - Late Breaking Papers, 2019

Isolation-Aware Timing Analysis and Design Space Exploration for Predictable and Composable Many-Core Systems.
Proceedings of the 31st Euromicro Conference on Real-Time Systems, 2019

Efficient Treatment of Uncertainty in System Reliability Analysis using Importance Measures.
Proceedings of the 49th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2019

In situ Statistics Generation within partially reconfigurable Hardware Accelerators for Query Processing.
Proceedings of the 15th International Workshop on Data Management on New Hardware, 2019

From Loop Fusion to Kernel Fusion: A Domain-Specific Approach to Locality Optimization.
Proceedings of the IEEE/ACM International Symposium on Code Generation and Optimization, 2019

Anytime instructions for programmable accuracy floating-point arithmetic.
Proceedings of the 16th ACM International Conference on Computing Frontiers, 2019

ReProVide: Towards Utilizing Heterogeneous Partially Reconfigurable Architectures for Near-Memory Data Processing.
Proceedings of the Datenbanksysteme für Business, 2019

DSL-Based Acceleration of Automotive Environment Perception and Mapping Algorithms for Embedded CPUs, GPUs, and FPGAs.
Proceedings of the Architecture of Computing Systems - ARCS 2019, 2019

2018
Loop Parallelization Techniques for FPGA Accelerator Synthesis.
Signal Processing Systems, 2018

A Design-Time/Run-Time Application Mapping Methodology for Predictable Execution Time in MPSoCs.
ACM Trans. Embedded Comput. Syst., 2018

Symbolic Multi-Level Loop Mapping of Loop Programs for Massively Parallel Processor Arrays.
ACM Trans. Embedded Comput. Syst., 2018

Symmetry-Eliminating Design Space Exploration for Hybrid Application Mapping on Many-Core Architectures.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

Reconfigurable Hardware Generation of Multigrid Solvers with Conjugate Gradient Coarse-Grid Solution.
Parallel Processing Letters, 2018

Automating the Development of High-Performance Multigrid Solvers.
Proceedings of the IEEE, 2018

Efficient Arithmetic Error Rate Calculus for Visibility Reduced Approximate Adders.
Embedded Systems Letters, 2018

Guest Editors' Introduction: Special Issue on Time-Critical Systems Design Part II.
IEEE Design & Test, 2018

Time-Critical Systems Design: A Survey.
IEEE Design & Test, 2018

Guest Editors' Introduction: Special Issue on Time-Critical Systems Design.
IEEE Design & Test, 2018

Integration of FPGAs in Database Management Systems: Challenges and Opportunities.
Datenbank-Spektrum, 2018

A predictive dynamic power management for LTE-Advanced mobile devices.
Proceedings of the 2018 IEEE Wireless Communications and Networking Conference, 2018

Base Algorithms of Environment Maps and Efficient Occupancy Grid Mapping on Embedded GPUs.
Proceedings of the 4th International Conference on Vehicle Technology and Intelligent Transport Systems, 2018

Automatic Optimization of Redundant Message Routings in Automotive Networks.
Proceedings of the 21st International Workshop on Software and Compilers for Embedded Systems, 2018

Automatic Kernel Fusion for Image Processing DSLs.
Proceedings of the 21st International Workshop on Software and Compilers for Embedded Systems, 2018

Reinforcement Learning for Power-Efficient Grant Prediction in LTE.
Proceedings of the 21st International Workshop on Software and Compilers for Embedded Systems, 2018

Configuration Tampering of BRAM-based AES Implementations on FPGAs.
Proceedings of the 2018 International Conference on ReConFigurable Computing and FPGAs, 2018

Model-Based Design Automation of Hardware/Software Co-Designs for Xilinx Zynq PSoCs.
Proceedings of the 2018 International Conference on ReConFigurable Computing and FPGAs, 2018

Run-time Requirement Enforcement for Loop Programs on Processor Arrays.
Proceedings of the 16th ACM/IEEE International Conference on Formal Methods and Models for System Design, 2018

On the Complexity of Mapping Feasibility in Many-Core Architectures.
Proceedings of the 12th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2018

Can Approximate Computing Reduce Power Consumption on FPGAs?
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

Dynamic resource management for heterogeneous many-cores.
Proceedings of the International Conference on Computer-Aided Design, 2018

Design space exploration of multi-output logic function approximations.
Proceedings of the International Conference on Computer-Aided Design, 2018

AConFPGA: A Multiple-Output Boolean Function Approximation DSE Technique Targeting FPGAs.
Proceedings of the International Conference on Field-Programmable Technology, 2018

Cell-based update algorithm for occupancy grid maps and hybrid map for ADAS on embedded GPUs.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Optimistic regular expression matching on FPGAs for near-data processing.
Proceedings of the 14th International Workshop on Data Management on New Hardware, 2018

Architecture decomposition in system synthesis of heterogeneous many-core systems.
Proceedings of the 55th Annual Design Automation Conference, 2018

Probabilistic Dominance in Robust Multi-Objective Optimization.
Proceedings of the 2018 IEEE Congress on Evolutionary Computation, 2018

Invasive Computing for Predictability of Multiple Non-functional Properties: A Cyber-Physical System Case Study.
Proceedings of the 29th IEEE International Conference on Application-specific Systems, 2018

Solving Maxwell's Equations with Modern C++ and SYCL: A Case Study.
Proceedings of the 29th IEEE International Conference on Application-specific Systems, 2018

Symbolic Parallelization of Nested Loop Programs
Springer, ISBN: 978-3-319-73909-0, 2018

2017
Introduction to Hardware/Software Codesign.
Proceedings of the Handbook of Hardware/Software Codesign., 2017

Hybrid Optimization Techniques for System-Level Design Space Exploration.
Proceedings of the Handbook of Hardware/Software Codesign., 2017

SysteMoC: A Data-Flow Programming Language for Codesign.
Proceedings of the Handbook of Hardware/Software Codesign., 2017

A Novel Image Impulse Noise Removal Algorithm Optimized for Hardware Accelerators.
Signal Processing Systems, 2017

Automatic Reliability Analysis in the Presence of Probabilistic Common Cause Failures.
IEEE Trans. Reliability, 2017

Noc-HMP: A Heterogeneous Multicore Processor for Embedded Systems Designed in SystemJ.
ACM Trans. Design Autom. Electr. Syst., 2017

Power Density-Aware Resource Management for Heterogeneous Tiled Multicores.
IEEE Trans. Computers, 2017

On the Boolean extension of the Birnbaum importance to non-coherent systems.
Rel. Eng. & Sys. Safety, 2017

Towards the co-evolution of industrial products and its production systems by combining models from development and hardware/software deployment in cyber-physical systems.
Production Engineering, 2017

Efficient task spawning for shared memory and message passing in many-core architectures.
Journal of Systems Architecture - Embedded Systems Design, 2017

Using design space exploration for finding schedules with guaranteed reaction times of synchronous programs on multi-core architecture.
Journal of Systems Architecture - Embedded Systems Design, 2017

Optimizing scrubbing by netlist analysis for FPGA configuration bit classification and floorplanning.
Integration, 2017

A Scala prototype to generate multigrid solver implementations for different problems and target multi-core platforms.
IJCSE, 2017

Self-Adaptive FPGA-Based Image Processing Filters Using Approximate Arithmetics.
Proceedings of the 20th International Workshop on Software and Compilers for Embedded Systems, 2017

Automatic Conversion of Simulink Models to SysteMoC Actor Networks.
Proceedings of the 20th International Workshop on Software and Compilers for Embedded Systems, 2017

Exploiting Predictability in Dynamic Network Communication for Power-Efficient Data Transmission in LTE Radio Systems.
Proceedings of the 20th International Workshop on Software and Compilers for Embedded Systems, 2017

Predictable run-time mapping reconfiguration for real-time applications on many-core systems.
Proceedings of the 25th International Conference on Real-Time Networks and Systems, 2017

Constructing fast and cycle-accurate simulators for configurable accelerators using C++ templates.
Proceedings of the International Symposium on Rapid System Prototyping, 2017

A reconfigurable memory architecture for system integration of coarse-grained reconfigurable arrays.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2017

TCPA editor: A design automation environment for a class of coarse-grained reconfigurable arrays.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2017

Orthogonal Instruction Processing: An Alternative to Lightweight VLIW Processors.
Proceedings of the 11th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2017

Redundancy-aware Design Space Exploration for Memory Reliability in Many-cores.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, 2017

Auto-vectorization for image processing DSLs.
Proceedings of the 18th ACM SIGPLAN/SIGBED Conference on Languages, 2017

Convoy tracking for ADAS on embedded GPUs.
Proceedings of the IEEE Intelligent Vehicles Symposium, 2017

High-Level Synthesis for Hardware/Software Co-Design of Distributed Smart Camera Systems.
Proceedings of the 11th International Conference on Distributed Smart Cameras, 2017

Generating FPGA-based image processing accelerators with Hipacc: (Invited paper).
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

High performance network-on-chip simulation by interval-based timing predictions.
Proceedings of the 15th IEEE/ACM Symposium on Embedded Systems for Real-Time Multimedia, 2017

System-level reliability analysis considering imperfect fault coverage.
Proceedings of the 15th IEEE/ACM Symposium on Embedded Systems for Real-Time Multimedia, 2017

Formal timing analysis of non-scheduled traffic in automotive scheduled TSN networks.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Automatic operating point distillation for hybrid mapping methodologies.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Optimizing Message Routing and Scheduling in Automotive Mixed-Criticality Time-Triggered Networks.
Proceedings of the 54th Annual Design Automation Conference, 2017

Hardware design and analysis of efficient loop coarsening and border handling for image processing.
Proceedings of the 28th IEEE International Conference on Application-specific Systems, 2017

Efficiency in ILP processing by using orthogonality.
Proceedings of the 28th IEEE International Conference on Application-specific Systems, 2017

2016
Systems of Partial Differential Equations in ExaSlang.
Proceedings of the Software for Exascale Computing - SPPEXA 2013-2015, 2016

FPGA-Based Dynamically Reconfigurable SQL Query Processing.
TRETS, 2016

HIPAcc: A Domain-Specific Language and Compiler for Image Processing.
IEEE Trans. Parallel Distrib. Syst., 2016

Hierarchical Statistical Leakage Analysis and Its Application.
ACM Trans. Design Autom. Electr. Syst., 2016

Invasive computing for timing-predictable stream processing on MPSoCs.
it - Information Technology, 2016

Invasive computing.
it - Information Technology, 2016

Providing fault tolerance through invasive computing.
it - Information Technology, 2016

A new time-independent reliability importance measure.
European Journal of Operational Research, 2016

Recap of the 2016 DATE Conference & Exhibition.
IEEE Design & Test, 2016

Adaptive Isolation for Predictability and Security (Dagstuhl Seminar 16441).
Dagstuhl Reports, 2016

Design-Time/Run-Time Mapping of Security-Critical Applications in Heterogeneous MPSoCs.
Proceedings of the 19th International Workshop on Software and Compilers for Embedded Systems, 2016

A Binary Time Series Model of LTE Scheduling for Machine Learning Prediction.
Proceedings of the 2016 IEEE 1st International Workshops on Foundations and Applications of Self* Systems (FAS*W), 2016

Hybrid code description for developing fast and resource efficient image processing architectures.
Proceedings of the International Conference on Embedded Computer Systems: Architectures, 2016

ReOrder: Runtime datapath generation for high-throughput multi-stream processing.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2016

Hybrid energy-aware reconfiguration management on Xilinx Zynq SoCs.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2016

ActorX10: an actor library for X10.
Proceedings of the 6th ACM SIGPLAN Workshop on X10, 2016

Multi-objective design space exploration for the optimization of the HEVC mode decision process.
Proceedings of the 2016 Picture Coding Symposium, 2016

Language and Compilation of Parallel Programs for *-Predictable MPSoC Execution Using Invasive Computing.
Proceedings of the 10th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2016

Optimizing Latencies and Customizing NoC of Time-Predictable Heterogeneous Multi-core Processor.
Proceedings of the 10th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2016

Exploration of Power Domain Partitioning for Application-Specific SoCs in System-Level Design.
Proceedings of the 19th GI/ITG/GMM Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, 2016

Modeling, programming and performance analysis of automotive environment map representations on embedded GPUs.
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2016

FAU: Fast and error-optimized approximate adder units on LUT-Based FPGAs.
Proceedings of the 2016 International Conference on Field-Programmable Technology, 2016

FPGA-based accelerator design from a domain-specific language.
Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

A LUT-Based Approximate Adder.
Proceedings of the 24th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2016

A heterogeneous multi-core SoC for mixed criticality industrial automation systems.
Proceedings of the 21st IEEE International Conference on Emerging Technologies and Factory Automation, 2016

Guiding Genetic Algorithms using importance measures for reliable design of embedded systems.
Proceedings of the 2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2016

Formal reliability analysis of switched ethernet automotive networks under transient transmission errors.
Proceedings of the 53rd Annual Design Automation Conference, 2016

Modulo scheduling of symbolically tiled loops for tightly coupled processor arrays.
Proceedings of the 27th IEEE International Conference on Application-specific Systems, 2016

Analysis and Exploitation of CTU-Level Parallelism in the HEVC Mode Decision Process Using Actor-Based Modeling.
Proceedings of the Architecture of Computing Systems - ARCS 2016, 2016

HIPAcc.
Proceedings of the FPGAs for Software Programmers, 2016

2015
Automatic communication-driven virtual prototyping and design for networked embedded systems.
Microprocessors and Microsystems - Embedded Hardware Design, 2015

Synthesis and optimization of image processing accelerators using domain knowledge.
Journal of Systems Architecture - Embedded Systems Design, 2015

Resource-awareness on heterogeneous MPSoCs for image processing.
Journal of Systems Architecture - Embedded Systems Design, 2015

Techniques for on-demand structural redundancy for massively parallel processor arrays.
Journal of Systems Architecture - Embedded Systems Design, 2015

Application-aware cross-layer reliability analysis and optimization.
it - Information Technology, 2015

Adaptive Isolation for Predictable MPSoC Stream Processing.
Proceedings of the 18th International Workshop on Software and Compilers for Embedded Systems, 2015

Runtime Adaptation of Application Execution under Thermal and Power Constraints in Massively Parallel Processor Arrays.
Proceedings of the 18th International Workshop on Software and Compilers for Embedded Systems, 2015

Throughput-optimizing Compilation of Dataflow Applications for Multi-Cores using Quasi-Static Scheduling.
Proceedings of the 18th International Workshop on Software and Compilers for Embedded Systems, 2015

Symbolic loop parallelization for balancing I/O and memory accesses on processor arrays.
Proceedings of the 13. ACM/IEEE International Conference on Formal Methods and Models for Codesign, 2015

Symbolic Message Routing for Multi-Objective Optimization of Automotive E/E Architecture Component Platforms.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, 2015

Design Methodology and Run-Time Management for Predictable Many-Core Systems.
Proceedings of the 2015 IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing Workshops, 2015

Reconfigurable Buffer Structures for Coarse-Grained Reconfigurable Arrays.
Proceedings of the System Level Design from HW/SW to Memory for Embedded Systems, 2015

A co-design approach for accelerated SQL query processing via FPGA-based data filtering.
Proceedings of the 2015 International Conference on Field Programmable Technology, 2015

Invasive computing for predictable stream processing: a simulation-based case study.
Proceedings of the 13th IEEE Symposium on Embedded Systems For Real-time Multimedia, 2015

Quasi-static scheduling of data flow graphs in the presence of limited channel capacities.
Proceedings of the 13th IEEE Symposium on Embedded Systems For Real-time Multimedia, 2015

Formal analysis of the startup delay of SOME/IP service discovery.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Uncertainty-aware reliability analysis and optimization.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Execution-driven parallel simulation of PGAS applications on heterogeneous tiled architectures.
Proceedings of the 52nd Annual Design Automation Conference, 2015

Robust design of E/E architecture component platforms.
Proceedings of the 52nd Annual Design Automation Conference, 2015

On-demand fault-tolerant loop processing on massively parallel processor arrays.
Proceedings of the 26th IEEE International Conference on Application-specific Systems, 2015

Loop coarsening in C-based High-Level Synthesis.
Proceedings of the 26th IEEE International Conference on Application-specific Systems, 2015

Network Interface with Task Spawning Support for NoC-Based DSM Architectures.
Proceedings of the Architecture of Computing Systems - ARCS 2015, 2015

Adaptive fault tolerance through invasive computing.
Proceedings of the 2015 NASA/ESA Conference on Adaptive Hardware and Systems, 2015

A co-design approach for fault-tolerant loop execution on Coarse-Grained Reconfigurable Arrays.
Proceedings of the 2015 NASA/ESA Conference on Adaptive Hardware and Systems, 2015

Fault-tolerant communication in invasive networks on chip.
Proceedings of the 2015 NASA/ESA Conference on Adaptive Hardware and Systems, 2015

Reliability of space-grade vs. COTS SRAM-based FPGA in N-modular redundancy.
Proceedings of the 2015 NASA/ESA Conference on Adaptive Hardware and Systems, 2015

2014
Symbolic Mapping of Loop Programs onto Processor Arrays.
Signal Processing Systems, 2014

Compact Code Generation for Tightly-Coupled Processor Arrays.
Signal Processing Systems, 2014

MAESTRO - Holistic Actor-Oriented Modeling of Nonfunctional Properties and Firmware Behavior for MPSoCs.
ACM Trans. Design Autom. Electr. Syst., 2014

Introduction to the Special Issue on Domain-Specific Multicore Computing.
ACM Trans. Embedded Comput. Syst., 2014

Experiments on Optimizing the Performance of Stencil Codes with SPL Conqueror.
Parallel Processing Letters, 2014

Resilience Articulation Point (RAP): Cross-layer dependability modeling for nanometer system-on-chip resilience.
Microelectronics Reliability, 2014

Towards a performance-portable description of geometric multigrid algorithms using a domain-specific language.
J. Parallel Distrib. Comput., 2014

DPSK modulated wakeup mechanism for point-to-point networks with partial network support.
Proceedings of the 9th IEEE International Symposium on Industrial Embedded Systems, 2014

ExaSlang: a domain-specific language for highly scalable multigrid solvers.
Proceedings of the Fourth International Workshop on Domain-Specific Languages and High-Level Frameworks for High Performance Computing, 2014

Self-Integration for Virtualization of Embedded Many-Core Systems.
Proceedings of the Eighth IEEE International Conference on Self-Adaptive and Self-Organizing Systems Workshops, 2014

Parametric yield optimization using leakage-yield-driven floorplanning.
Proceedings of the 24th International Workshop on Power and Timing Modeling, 2014

End-to-end power estimation for heterogeneous cellular LTE SoCs in early design phases.
Proceedings of the 24th International Workshop on Power and Timing Modeling, 2014

Symbolic inner loop parallelisation for massively parallel processor arrays.
Proceedings of the Twelfth ACM/IEEE International Conference on Formal Methods and Models for Codesign, 2014

Minimizing Scrubbing Effort through Automatic Netlist Partitioning and Floorplanning.
Proceedings of the 2014 IEEE International Parallel & Distributed Processing Symposium Workshops, 2014

An Evaluation of Domain-Specific Language Technologies for Code Generation.
Proceedings of the 2014 14th International Conference on Computational Science and Its Applications, Guimaraes, Portugal, June 30, 2014

An image processing library for C-based high-level synthesis.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

Energy-aware SQL query acceleration through FPGA-based dynamic partial reconfiguration.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

An automatic netlist and floorplanning approach to improve the MTTR of scrubbing techniques (abstract only).
Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2014

A Self-Adaptive SEU Mitigation System for FPGAs with an Internal Block RAM Radiation Particle Sensor.
Proceedings of the 22nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2014

ExaStencils: Advanced Stencil-Code Engineering.
Proceedings of the Euro-Par 2014: Parallel Processing Workshops, 2014

Communication-Driven Automatic Virtual Prototyping for Networked Embedded Systems.
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014

Runtime Reconfigurable Bus Arbitration for Concurrent Applications on Heterogeneous MPSoC Architectures.
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014

Design Space Exploration for Automotive E/E Architecture Component Platforms.
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014

Model-based actor multiplexing with application to complex communication protocols.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Multi-objective distributed run-time resource management for many-cores.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

A self-propagating wakeup mechanism for point-to-point networks with partial network support.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Code generation for embedded heterogeneous architectures on android.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Multi-variant-based design space exploration for automotive embedded systems.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Non-intrusive integration of advanced diagnosis features in automotive E/E-architectures.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Self-adaptive harris corner detector on heterogeneous many-core processor.
Proceedings of the 2014 Conference on Design and Architectures for Signal and Image Processing, 2014

Advanced Diagnosis: SBST and BIST Integration in Automotive E/E Architectures.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

Multi-Objective Local-Search Optimization using Reliability Importance Measuring.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

CAP: Communication Aware Programming.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

DAARM: Design-time application analysis and run-time mapping for predictable execution in many-core systems.
Proceedings of the 2014 International Conference on Hardware/Software Codesign and System Synthesis, 2014

Code generation from a domain-specific language for C-based HLS of hardware accelerators.
Proceedings of the 2014 International Conference on Hardware/Software Codesign and System Synthesis, 2014

Towards scalable symbolic routing for multi-objective networked embedded system design and optimization.
Proceedings of the 2014 International Conference on Hardware/Software Codesign and System Synthesis, 2014

An efficient technique for computing importance measures in automatic design of dependable embedded systems.
Proceedings of the 2014 International Conference on Hardware/Software Codesign and System Synthesis, 2014

Domain-specific augmentations for High-Level Synthesis.
Proceedings of the IEEE 25th International Conference on Application-Specific Systems, 2014

Quality-aware video decoding on thermally-constrained MPSoC platforms.
Proceedings of the IEEE 25th International Conference on Application-Specific Systems, 2014

Mahler: Sketch-Based Model-Driven Virtual Prototyping.
Proceedings of the Architecture of Computing Systems - ARCS 2014, 2014

Towards Actor-oriented Programming on PGAS-based Multicore Architectures.
Proceedings of the ARCS 2014, 2014

The Invasive Network on Chip - A Multi-Objective Many-Core Communication Infrastructure.
Proceedings of the ARCS 2014, 2014

Application-driven reconfiguration of shared resources for timing predictability of MPSoC platforms.
Proceedings of the 48th Asilomar Conference on Signals, Systems and Computers, 2014

Exploration of Distributed Automotive Systems Using Compositional Timing Analysis.
Proceedings of the Embedded Systems Development, From Functional Models to Implementations, 2014

Design and Evaluation of Future Ethernet AVB-Based ECU Networks.
Proceedings of the Embedded Systems Development, From Functional Models to Implementations, 2014

2013
Integrated Modeling Using Finite State Machines and Dataflow Graphs.
Proceedings of the Handbook of Signal Processing Systems, 2013

Virtual networks - distributed communication resource management.
TRETS, 2013

A rule-based quasi-static scheduling approach for static islands in dynamic dataflow graphs.
ACM Trans. Embedded Comput. Syst., 2013

Symbolic system-level design methodology for multi-mode reconfigurable systems.
Design Autom. for Emb. Sys., 2013

NoC simulation in heterogeneous architectures for PGAS programming model.
Proceedings of the International Workshop on Software and Compilers for Embedded Systems, 2013

Real-timerange image preprocessing on FPGAs.
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2013

Exploitation of Quality/Throughput Tradeoffs in Image Processing through Invasive Computing.
Proceedings of the Parallel Computing: Accelerating Computational Science and Engineering (CSE), 2013

High-Level Synthesis Revised - Generation of FPGA Accelerators from a Domain-Specific Language using the Polyhedron Model.
Proceedings of the Parallel Computing: Accelerating Computational Science and Engineering (CSE), 2013

Model-Based Representation of Schedules for Dataflow Graphs.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2013

Investigating the Impact of Energy-Efficient Ethernet on Automotive Applications via High-level Modeling.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2013

Hardware Supported Adaptive Data Collection for Networks on Chip.
Proceedings of the 2013 IEEE International Symposium on Parallel & Distributed Processing, 2013

Bridging algorithm and ESL design: Matlab/Simulink model transformation and validation.
Proceedings of the 2013 Forum on specification and Design Languages, 2013

Representing mapping and scheduling decisions within dataflow graphs.
Proceedings of the 2013 Forum on specification and Design Languages, 2013

Acceleration of SQL Restrictions and Aggregations through FPGA-Based Dynamic Partial Reconfiguration.
Proceedings of the 21st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2013

Timing analysis of Ethernet AVB-based automotive E/E architectures.
Proceedings of 2013 IEEE 18th Conference on Emerging Technologies & Factory Automation, 2013

AUTO-GS: Self-Optimization of NoC Traffic through Hardware Managed Virtual Connections.
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

Game-theoretic analysis of decentralized core allocation schemes on many-core systems.
Proceedings of the Design, Automation and Test in Europe, 2013

Automatic success tree-based reliability analysis for the consideration of transient and permanent faults.
Proceedings of the Design, Automation and Test in Europe, 2013

A prototype of an adaptive computer vision algorithm on MPSoC architecture.
Proceedings of the 2013 Conference on Design and Architectures for Signal and Image Processing, 2013

Accuracy and performance analysis of Harris Corner computation on tightly-coupled processor arrays.
Proceedings of the 2013 Conference on Design and Architectures for Signal and Image Processing, 2013

On robust task-accurate performance estimation.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

Run-time adaption for highly-complex multi-core systems.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2013

IVaM: Implicit variant modeling and management for automotive embedded systems.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2013

System integration of tightly-coupled processor arrays using reconfigurable buffer structures.
Proceedings of the Computing Frontiers Conference, 2013

Symbolic parallelization of loop programs for massively parallel processor arrays.
Proceedings of the 24th International Conference on Application-Specific Systems, 2013

Loop program mapping and compact code generation for programmable hardware accelerators.
Proceedings of the 24th International Conference on Application-Specific Systems, 2013

HW/SW Tradeoffs for Dynamic Message Scheduling in Controller Area Network (CAN).
Proceedings of the Architecture of Computing Systems - ARCS 2013, 2013

On Confident Task-Accurate Performance Estimation.
Proceedings of the Architecture of Computing Systems - ARCS 2013, 2013

2012
Dynamic Defragmentation of Reconfigurable Devices.
TRETS, 2012

Hierarchical power management for adaptive tightly-coupled processor arrays.
ACM Trans. Design Autom. Electr. Syst., 2012

Model-Based Virtual Prototype Acceleration.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2012

Hardware/Software Codesign: The Past, the Present, and Predicting the Future.
Proceedings of the IEEE, 2012

Placing Multimode Streaming Applications on Dynamically Partially Reconfigurable Architectures.
Int. J. Reconfig. Comp., 2012

Distributed self-organizing bandwidth allocation for priority-based bus communication.
Concurrency and Computation: Practice and Experience, 2012

Fast architecture evaluation of heterogeneous MPSoCs by host-compiled simulation.
Proceedings of the Workshop on Software and Compilers for Embedded Systems, 2012

Towards Domain-Specific Computing for Stencil Codes in HPC.
Proceedings of the 2012 SC Companion: High Performance Computing, 2012

Virtual prototyping for efficient multi-core ECU development of driver assistance systems.
Proceedings of the 2012 International Conference on Embedded Computer Systems: Architectures, 2012

A co-simulation approach for system-level analysis of embedded control systems.
Proceedings of the 2012 International Conference on Embedded Computer Systems: Architectures, 2012

Cross-Level Compositional Reliability Analysis for Embedded Systems.
Proceedings of the Computer Safety, Reliability, and Security, 2012

FPGA-based testbed for timing behavior evaluation of the Controller Area Network (CAN).
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2012

Actor-oriented Modeling und Simulation of Cut-through Communication in Network Controllers.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2012

Exploiting Model-Knowledge in High-Level Synthesis.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2012

Unreliable Data Transmissions und Limited Hardware Communication Buffers in Automotive E/E Virtual Prototypes.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2012

Automatic Optimization of In-Flight Memory Transactions for GPU Accelerators Based on a Domain-Specific Language for Medical Imaging.
Proceedings of the 11th International Symposium on Parallel and Distributed Computing, 2012

Generating Device-specific GPU Code for Local Operators in Medical Imaging.
Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium, 2012

Hardware-assisted Decentralized Resource Management for Networks on Chip with QoS.
Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012

Invasive computing - Concepts and overheads.
Proceedings of the Proceeding of the 2012 Forum on Specification and Design Languages, 2012

Power Management Strategies for Serial RapidIO Endpoints in FPGAs.
Proceedings of the 2012 IEEE 20th Annual International Symposium on Field-Programmable Custom Computing Machines, 2012

On-the-fly Composition of FPGA-Based SQL Query Accelerators Using a Partially Reconfigurable Module Library.
Proceedings of the 2012 IEEE 20th Annual International Symposium on Field-Programmable Custom Computing Machines, 2012

Mastering Software Variant Explosion for GPU Accelerators.
Proceedings of the Euro-Par 2012: Parallel Processing Workshops, 2012

Variation-aware leakage power model extraction for system-level hierarchical power analysis.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Designing FlexRay-based automotive architectures: A holistic OEM approach.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

A prototype of an invasive tightly-coupled processor array.
Proceedings of the 2012 Conference on Design and Architectures for Signal and Image Processing, 2012

Considering diagnosis functionality during automatic system-level design of automotive networks.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

FlexRay Static Segment Scheduling.
Proceedings of the Advances in Real-Time Systems (to Georg Färber on the occasion of his appointment as Professor Emeritus at TU München after leading the Lehrstuhl für Realzeit-Computersysteme for 34 illustrious years)., 2012

Approximate time functional simulation of resource-aware programming concepts for heterogeneous MPSoCs.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

Design of Low Power On-chip Processor Arrays.
Proceedings of the 23rd IEEE International Conference on Application-Specific Systems, 2012

A Very Fast and Quasi-accurate Power-State-Based System-Level Power Modeling Methodology.
Proceedings of the Architecture of Computing Systems - ARCS 2012 - 25th International Conference, Munich, Germany, February 28, 2012

Dynamic Task-Scheduling and Resource Management for GPU Accelerators in Medical Imaging.
Proceedings of the Architecture of Computing Systems - ARCS 2012 - 25th International Conference, Munich, Germany, February 28, 2012

Partial Reconfiguration on FPGAs in Practice - Tools and Applications.
Proceedings of the ARCS 2012 Workshops, 28. Februar - 2. März 2012, München, Germany, 2012

Keynote address II: Exploiting dynamic hardware reconfigurability for efficiency, performance, and reliability.
Proceedings of the 2012 NASA/ESA Conference on Adaptive Hardware and Systems, 2012

2011
A co-simulation approach for control performance analysis during design space exploration of cyber-physical systems.
SIGBED Review, 2011

Efficient Evaluation of Power/Area/Latency Design Trade-Offs for Coarse-Grained Reconfigurable Processor Arrays.
J. Low Power Electronics, 2011

Scalable Many-Domain Power Gating in Coarse-Grained Reconfigurable Processor Arrays.
Embedded Systems Letters, 2011

Testing switched Ethernet networks in automotive embedded systems.
Proceedings of the Industrial Embedded Systems (SIES), 2011

Resource-aware programming and simulation of MPSoC architectures through extension of X10.
Proceedings of the 14th International Workshop on Software and Compilers for Embedded Systems, 2011

Frameworks for GPU Accelerators: A comprehensive evaluation using 2D/3D image registration.
Proceedings of the IEEE 9th Symposium on Application Specific Processors, 2011

Calibration and validation of software performance models for pedestrian detection systems.
Proceedings of the 2011 International Conference on Embedded Computer Systems: Architectures, 2011

Automatic generation of system-level virtual prototypes from streaming application models.
Proceedings of the 22nd IEEE International Symposium on Rapid System Prototyping, 2011

Towards Symbolic Run-Time Reconfiguration in Tightly-Coupled Processor Arrays.
Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs, 2011

Dynamic decentralized mapping of tree-structured applications on NoC architectures.
Proceedings of the NOCS 2011, 2011

Detector defect correction of medical images on graphics processors.
Proceedings of the Medical Imaging 2011: Image Processing, 2011

Towards Resource Aware Programming on Intel's Single-Chip Cloud Computer Processor.
Proceedings of the 3rd Many-core Applications Research Community (MARC) Symposium. Proceedings of the 3rd MARC Symposium, 2011

Distributed Resource Reservation in Massively Parallel Processor Arrays.
Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011

Bitonic Sorting on Dynamically Reconfigurable Architectures.
Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011

Opt4J: a modular framework for meta-heuristic optimization.
Proceedings of the 13th Annual Genetic and Evolutionary Computation Conference, 2011

An FPGA implementation of a threat-based strategy for Connect6.
Proceedings of the 2011 International Conference on Field-Programmable Technology, 2011

Operational mode exploration for reconfigurable systems with multiple applications.
Proceedings of the 2011 International Conference on Field-Programmable Technology, 2011

Runtime stress-aware replica placement on reconfigurable devices under safety constraints.
Proceedings of the 2011 International Conference on Field-Programmable Technology, 2011

Unifying Partitioning and Placement for SAT-Based Exploration of Heterogeneous Reconfigurable SoCs.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2011

Stress-Aware Module Placement on Reconfigurable Devices.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2011

ESL power and performance estimation for heterogeneous MPSOCS using SystemC.
Proceedings of the 2011 Forum on Specification & Design Languages, 2011

DynOAA - Dynamic offset adaptation algorithm for improving response times of CAN systems.
Proceedings of the Design, Automation and Test in Europe, 2011

An automated data structure migration concept - From CAN to Ethernet/IP in automotive embedded systems (CANoverIP).
Proceedings of the Design, Automation and Test in Europe, 2011

A rule-based static dataflow clustering algorithm for efficient embedded software synthesis.
Proceedings of the Design, Automation and Test in Europe, 2011

Symbolic system synthesis in the presence of stringent real-time constraints.
Proceedings of the 48th Design Automation Conference, 2011

Accuracy of ethernet AVB time synchronization under varying temperature conditions for automotive networks.
Proceedings of the 48th Design Automation Conference, 2011

Symbolic design space exploration for multi-mode reconfigurable systems.
Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis, 2011

Mapping of applications to MPSoCs.
Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis, 2011


Self-organized Message Scheduling for Asynchronous Distributed Embedded Systems.
Proceedings of the Autonomic and Trusted Computing - 8th International Conference, 2011

Decentralized dynamic resource management support for massively parallel processor arrays.
Proceedings of the 22nd IEEE International Conference on Application-specific Systems, 2011

Frameworks for Multi-core Architectures: A Comprehensive Evaluation Using 2D/3D Image Registration.
Proceedings of the Architecture of Computing Systems - ARCS 2011, 2011

Gateway Strategies for Embedding of Automotive CAN-Frames into Ethernet-Packets and Vice Versa.
Proceedings of the Architecture of Computing Systems - ARCS 2011, 2011

Design of Image Processing Embedded Systems Using Multidimensional Data Flow
Embedded Systems, Springer, ISBN: 978-1-4419-7181-4, 2011

Invasive Computing: An Overview.
Proceedings of the Multiprocessor System-on-Chip - Hardware Design and Tool Integration., 2011

OrganicBus: Organic Self-organising Bus-Based Communication Systems.
Proceedings of the Organic Computing - A Paradigm Shift for Complex Systems, 2011

2010
Analysis of SystemC actor networks for efficient synthesis.
ACM Trans. Embedded Comput. Syst., 2010

Selected papers from the 18th International Conference on Field Programmable Logic and Applications (FPL 2008) [Editorial].
IET Computers & Digital Techniques, 2010

A system-level synthesis approach from formal application models to generic bus-based MPSoCs.
Proceedings of the 2010 International Conference on Embedded Computer Systems: Architectures, 2010

Placing Streaming Applications with Similarities on Dynamically Partially Reconfigurable Architectures.
Proceedings of the ReConFig'10: 2010 International Conference on Reconfigurable Computing and FPGAs, 2010

Actor-oriented Modeling of Driver Assistance Systems for Efficient Multi-Core ECU Implementation.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2010

Integrating Hardware/Firmware Verification Efforts Using SystemC High-Level Models.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2010

A Self-Organizing Distributed Reinforcement Learning Algorithm to Achieve Fair Bandwidth Allocation for Priority-Based Bus Communication.
Proceedings of the 13th IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing Workshops, 2010

Adaptive traffic scheduling techniques for mixed real-time and streaming applications on reconfigurable hardware.
Proceedings of the 24th IEEE International Symposium on Parallel and Distributed Processing, 2010

Virtual area management: Multitasking on dynamically partially reconfigurable devices.
Proceedings of the 24th IEEE International Symposium on Parallel and Distributed Processing, 2010

Network Bandwidth Optimization of Ethernet-Based Streaming Applications in Automotive Embedded Systems.
Proceedings of the 19th International Conference on Computer Communications and Networks, 2010

Symbolic system level reliability analysis.
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

Multiplexing Methods for Power Watermarking.
Proceedings of the HOST 2010, 2010

A deeply pipelined and parallel architecture for denoising medical images.
Proceedings of the International Conference on Field-Programmable Technology, 2010

A Bus-Based SoC Architecture for Flexible Module Placement on Reconfigurable FPGAs.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2010

Using the Power Side Channel of FPGAs for Communication.
Proceedings of the 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2010

Interprocedural Placement-Aware Configuration Prefetching for FPGA-Based Systems.
Proceedings of the 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2010

Generating GPU Code from a High-Level Representation for Image Processing Kernels.
Proceedings of the Euro-Par 2011: Parallel Processing Workshops - CCPI, CGWS, HeteroPar, HiBB, HPCVirt, HPPC, HPSS, MDGS, ProPer, Resilience, UCHPC, VHPC, Bordeaux, France, August 29, 2010

Model-based analysis, synthesis and testing of automotive hardware/software architectures.
Proceedings of the 10th International conference on Embedded software, 2010

Efficient High-Level modeling in the networking domain.
Proceedings of the Design, Automation and Test in Europe, 2010

A rapid prototyping system for error-resilient multi-processor systems-on-chip.
Proceedings of the Design, Automation and Test in Europe, 2010

Robust design of embedded systems.
Proceedings of the Design, Automation and Test in Europe, 2010

New Directions for IP Core Watermarking and Identification.
Proceedings of the Dynamically Reconfigurable Architectures, 11.07. - 16.07.2010, 2010

10281 Summary - Dynamically Reconfigurable Architectures.
Proceedings of the Dynamically Reconfigurable Architectures, 11.07. - 16.07.2010, 2010

10281 Abstracts Collection - Dynamically Reconfigurable Architectures.
Proceedings of the Dynamically Reconfigurable Architectures, 11.07. - 16.07.2010, 2010

Towards scalable system-level reliability analysis.
Proceedings of the 47th Design Automation Conference, 2010

Improving platform-based system synthesis by satisfiability modulo theories solving.
Proceedings of the 8th International Conference on Hardware/Software Codesign and System Synthesis, 2010

Self-organizing Computer Vision for Robust Object Tracking in Smart Cameras.
Proceedings of the Autonomic and Trusted Computing - 7th International Conference, 2010

ReCoNets - Design Methodology for Embedded Systems Consisting of Small Networks of Reconfigurable Nodes and Connections.
Proceedings of the Dynamically Reconfigurable Systems - Architectures, 2010

Erlangen Slot Machine: An FPGA-Based Dynamically Reconfigurable Computing Platform.
Proceedings of the Dynamically Reconfigurable Systems - Architectures, 2010

ReCoNodes - Optimization Methods for Module Scheduling and Placement on Reconfigurable Hardware Devices.
Proceedings of the Dynamically Reconfigurable Systems - Architectures, 2010

Digitale Hardware/Software-Systeme: Spezifikation und Verifikation
eXamen.press, Springer, ISBN: 978-3-642-05355-9, 2010

Integrated Modeling using Finite State Machines and Dataflow Graphs.
Proceedings of the Handbook of Signal Processing Systems, 2010

2009
Hardware Decompression Techniques for FPGA-Based Embedded Systems.
TRETS, 2009

SystemCoDesigner - an automatic ESL synthesis approach by design space exploration and behavioral synthesis for streaming applications.
ACM Trans. Design Autom. Electr. Syst., 2009

Electronic System-Level Synthesis Methodologies.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2009

A holistic approach for tightly coupled reconfigurable parallel processors.
Microprocessors and Microsystems - Embedded Hardware Design, 2009

Concepts for run-time and error-resilient control flow checking of embedded RISC CPUs.
IJAACS, 2009

CODES+ISSS 2007 guest editors' introduction.
Design Autom. for Emb. Sys., 2009

Self-organizing Bandwidth Sharing in Priority-Based Medium Access.
Proceedings of the Third IEEE International Conference on Self-Adaptive and Self-Organizing Systems, 2009

Efficient Mapping of Multiresolution Image Filtering Algorithms on Graphics Processors.
Proceedings of the Embedded Computer Systems: Architectures, 2009

Testfallgenerierung für SystemC-Designs mit abstrakten Modellbeschreibungen.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2009

System Integration of Tightly-Coupled Reconfigurable Processor Arrays and Evaluation of Buffer Size Effects on Their Performance.
Proceedings of the ICPPW 2009, 2009

From dynamic reconfiguration to self-reconfiguration: Invasive algorithms and architectures.
Proceedings of the 2009 International Conference on Field-Programmable Technology, 2009

FPGA implementation of an invasive computing architecture.
Proceedings of the 2009 International Conference on Field-Programmable Technology, 2009

Self-organizing multi-cue fusion for FPGA-based embedded imaging.
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

General methodology for mapping iterative approximation algorithms to adaptive dynamically partially reconfigurable systems.
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

A communication architecture for complex runtime reconfigurable systems and its implementation on spartan-3 FPGAs.
Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, 2009

Efficient approximately-timed performance modeling for architectural exploration of MPSoCs.
Proceedings of the Forum on specification and Design Languages, 2009

Optimal Placement-aware Trace-Based Scheduling of Hardware Reconfigurations for FPGA Accelerators.
Proceedings of the FCCM 2009, 2009

Minimizing Internal Fragmentation by Fine-Grained Two-Dimensional Module Placement for Runtime Reconfiguralble Systems.
Proceedings of the FCCM 2009, 2009

CAN+: A new backward-compatible Controller Area Network (CAN) protocol with up to 16× higher data rates.
Proceedings of the Design, Automation and Test in Europe, 2009

Combined system synthesis and communication architecture exploration for MPSoCs.
Proceedings of the Design, Automation and Test in Europe, 2009

Model-based synthesis and optimization of static multi-rate image processing algorithms.
Proceedings of the Design, Automation and Test in Europe, 2009

Incorporating graceful degradation into embedded system design.
Proceedings of the Design, Automation and Test in Europe, 2009

Designing heterogeneous ECU networks via compact architecture encoding and hybrid timing analysis.
Proceedings of the 46th Design Automation Conference, 2009

FlexRay schedule optimization of the static segment.
Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, 2009

Exploiting data-redundancy in reliability-aware networked embedded system design.
Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, 2009

Acceleration of Multiresolution Imaging Algorithms: A Comparative Study.
Proceedings of the 20th IEEE International Conference on Application-Specific Systems, 2009

Impact of Loop Tiling on the Controller Logic of Acceleration Engines.
Proceedings of the 20th IEEE International Conference on Application-Specific Systems, 2009

Parallelization Approaches for Hardware Accelerators - Loop Unrolling Versus Loop Partitioning.
Proceedings of the Architecture of Computing Systems, 2009

Performance Matching of Hardware Acceleration Engines for Heterogeneous MPSoC Using Modular Performance Analysis.
Proceedings of the Architecture of Computing Systems, 2009

2008
Power Signature Watermarking of IP Cores for FPGAs.
Signal Processing Systems, 2008

Offline and Online Aspects of Defragmenting the Module Layout of a Partially Reconfigurable Device.
IEEE Trans. VLSI Syst., 2008

Invasive Algorithms and Architectures (Invasive Algorithmen und Architekturen).
it - Information Technology, 2008

Multi-objective routing and topology optimization in networked embedded systems.
Proceedings of the 2008 International Conference on Embedded Computer Systems: Architectures, 2008

Symbolic Reliability Analysis of Self-healing Networked Embedded Systems.
Proceedings of the Computer Safety, 2008

Co-design Architecture and Implementation for Point-Based Rendering on FPGAs.
Proceedings of the 19th IEEE/IFIP International Symposium on Rapid System Prototyping: RSP 2009, 2008

3D Person Tracking with a Color-Based Particle Filter.
Proceedings of the Robot Vision, Second International Workshop, 2008

A Feasibility-Preserving Crossover and Mutation Operator for Constrained Combinatorial Problems.
Proceedings of the Parallel Problem Solving from Nature, 2008

Power-Efficient Reconfiguration Control in Coarse-Grained Dynamically Reconfigurable Architectures.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2008

Classification of General Data Flow Actors into Known Models of Computation.
Proceedings of the 6th ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2008), 2008

Semi-Automatic Generation of mixed Hardware/Software Prototypes from Simulink Models.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2008

The PAULA Language for Designing Multi-Dimensional Dataflow-Intensive Applications.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2008

Symbolische Modellprüfung Aktor-orientierter High-level SystemC-Modelle mit Intervalldiagrammen.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2008

Heuristics for scheduling reconfigurable devices with consideration of reconfiguration overheads.
Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008

A Sequential Learning Resource Allocation Network for Image Processing Applications.
Proceedings of the 8th International Conference on Hybrid Intelligent Systems (HIS 2008), 2008

Netlist-level IP protection by watermarking for LUT-based FPGAs.
Proceedings of the 2008 International Conference on Field-Programmable Technology, 2008

Area and reconfiguration time minimization of the communication network in regular 2D reconfigurable architectures.
Proceedings of the FPL 2008, 2008

ReCoBus-Builder - A novel tool and technique to build statically and dynamically reconfigurable systems for FPGAS.
Proceedings of the FPL 2008, 2008

No-break dynamic defragmentation of reconfigurable devices.
Proceedings of the FPL 2008, 2008


A comparison of embedded reconfigurable video-processing architectures.
Proceedings of the FPL 2008, 2008


Symbolic Scheduling of SystemC Dataflow Designs.
Proceedings of the Languages for Embedded Systems and their Applications, 2008

Symbolic Quasi-Static Scheduling of Actor-Oriented SystemC Models.
Proceedings of the Forum on specification and Design Languages, 2008

Optimization of Routing and Reconfiguration Overhead in Programmable Processor Array Architectures.
Proceedings of the 16th IEEE International Symposium on Field-Programmable Custom Computing Machines, 2008

Efficient Reconfigurable On-Chip Buses for FPGAs.
Proceedings of the 16th IEEE International Symposium on Field-Programmable Custom Computing Machines, 2008

A generalized static data flow clustering algorithm for mpsoc scheduling of multimedia applications.
Proceedings of the 8th ACM & IEEE International conference on Embedded software, 2008

Communication Network Reconfiguration Overhead Optimization in Programmable Processor Array Architectures.
Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008

Utilization of all Levels of Parallelism in a Processor Array with Subword Parallelism.
Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008

Symbolic Reliability Analysis and Optimization of ECU Networks.
Proceedings of the Design, Automation and Test in Europe, 2008

Concurrent topology and routing optimization in automotive network integration.
Proceedings of the 45th Design Automation Conference, 2008

Symbolic voter placement for dependability-aware system synthesis.
Proceedings of the 6th International Conference on Hardware/Software Codesign and System Synthesis, 2008

A feasibility-preserving local search operator for constrained discrete optimization problems.
Proceedings of the IEEE Congress on Evolutionary Computation, 2008

Concepts for Autonomous Control Flow Checking for Embedded CPUs.
Proceedings of the Autonomic and Trusted Computing, 5th International Conference, 2008

Efficient symbolic multi-objective design space exploration.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

Topology-Aware Replica Placement in Fault-Tolerant Embedded Networks.
Proceedings of the Architecture of Computing Systems, 2008

Synthesis of Multi-dimensional High-Speed FIFOs for Out-of-Order Communication.
Proceedings of the Architecture of Computing Systems, 2008

Dynamic Reconfiguration of FlexRay Schedules for Response Time Reduction in Asynchronous Fault-Tolerant Networks.
Proceedings of the Architecture of Computing Systems, 2008

PARO: Synthesis of Hardware Accelerators for Multi-Dimensional Dataflow-Intensive Applications.
Proceedings of the Reconfigurable Computing: Architectures, 2008

Reconfigurable HW/SW Architecture of a Real-Time Driver Assistance System.
Proceedings of the Reconfigurable Computing: Architectures, 2008

Concepts for Self-Adaptive and Self-Healing Networked Embedded Systems.
Proceedings of the Organic Computing, 2008

2007
The Erlangen Slot Machine: A Dynamically Reconfigurable FPGA-based Computer.
VLSI Signal Processing, 2007

Design space exploration of reliable networked embedded systems.
Journal of Systems Architecture, 2007

Efficient control generation for mapping nested loop programs onto processor arrays.
Journal of Systems Architecture, 2007

Reconfigurable Computing Systems (Rekonfigurierbare Rechensysteme).
it - Information Technology, 2007

The Erlangen Slot Machine - A Platform for Interdisciplinary Research in Dynamically Reconfigurable Computing (ESM - Eine Hardware-Plattform für interdisziplinäre Forschung im Bereich des dynamischen rekonfigurierbaren Rechnens).
it - Information Technology, 2007

A SystemC-Based Design Methodology for Digital Signal Processing Systems.
EURASIP J. Emb. Sys., 2007

Dynamically Reconfigurable Architectures.
EURASIP J. Emb. Sys., 2007

Efficient event-driven simulation of parallel processor architectures.
Proceedings of the 10th International Workshop on Software and Compilers for Embedded Systems, 2007

Solving Multi-objective Pseudo-Boolean Problems.
Proceedings of the Theory and Applications of Satisfiability Testing, 2007

Simulative Buffer Analysis of Local Image Processing Algorithms Described by Windowed Synchronous Data Flow.
Proceedings of the 2007 International Conference on Embedded Computer Systems: Architectures, 2007

Massively Parallel Processor Architectures: A Co-design Approach.
Proceedings of the 3rd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2007

System Level Modeling and Performance Simulation for Dynamic Reconfigurable Computing Systems in SystemC.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2007

Modeling and Synthesis of Hardware-Software Morphing.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Bitstream Decompression for High Speed FPGA Configuration from Slow Memories.
Proceedings of the 2007 International Conference on Field-Programmable Technology, 2007

Efficient hardware checkpointing: concepts, overhead analysis, and implementation.
Proceedings of the ACM/SIGDA 15th International Symposium on Field Programmable Gate Arrays, 2007

Mapping Actor-Oriented Models to TLM Architectures.
Proceedings of the Forum on specification and Design Languages, 2007

Actor-Oriented Modeling and Simulation of Sliding Window Image Processing Algorithms.
Proceedings of the 2007 5th Workshop on Embedded Systems for Real-Time Multimedia, 2007

A Unified Retargetable Design Methodology for Dedicated and Re-Programmable Multiprocessor Arrays: Case Study and Quantitative Evaluation.
Proceedings of the 2007 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2007

Interactive presentation: Reliability-aware system synthesis.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

SAT-decoding in evolutionary algorithms for discrete constrained optimization problems.
Proceedings of the IEEE Congress on Evolutionary Computation, 2007

Modeling of Interconnection Networks in Massively Parallel Processor Architectures.
Proceedings of the Architecture of Computing Systems, 2007

Digitale Hardware/Software-Systeme: Synthese und Optimierung, 2. Auflage
eXamen.press, Springer, ISBN: 978-3-540-46822-6, 2007

2006
Mapping a class of dependence algorithms to coarse-grained reconfigurable arrays: architectural parameters and methodology.
IJES, 2006

Modeling and Design of Fault-Tolerant and Self-Adaptive Reconfigurable Networked Embedded Systems.
EURASIP J. Emb. Sys., 2006

Dynamic task binding for hardware/software reconfigurable networks.
Proceedings of the 19th Annual Symposium on Integrated Circuits and Systems Design, 2006

Multi-Objective Topology Optimization for Networked Embedded Systems.
Proceedings of 2006 International Conference on Embedded Computer Systems: Architectures, 2006

A Dynamically Reconfigurable Weakly Programmable Processor Array Architecture Template.
Proceedings of the 2nd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2006

Hierarchical Partitioning for Piecewise Linear Algorithms.
Proceedings of the Fifth International Conference on Parallel Computing in Electrical Engineering (PARELEC 2006), 2006

An Architecture Description Language for Massively Parallel Processor Architectures.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2006

Improving System Level Design Space Exploration by Incorporating SAT-Solvers into Multi-Objective Evolutionary Algorithms.
Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006

Modeling and Analysis of Windowed Synchronous Algorithms.
Proceedings of the 2006 IEEE International Conference on Acoustics Speech and Signal Processing, 2006

FPGA core watermarking based on power signature analysis.
Proceedings of the 2006 IEEE International Conference on Field Programmable Technology, 2006

A highly parameterizable parallel processor array architecture.
Proceedings of the 2006 IEEE International Conference on Field Programmable Technology, 2006

Identifying FPGA IP-Cores Based on Lookup Table Content Analysis.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

Minimizing Communication Cost for Reconfigurable Slot Modules.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

Efficient Representation and Simulation of Model-Based Designs.
Proceedings of the Forum on specification and Design Languages, 2006

Topic 18: Embedded Parallel Systems.
Proceedings of the Euro-Par 2006, Parallel Processing, 12th International Euro-Par Conference, Dresden, Germany, August 28, 2006

Searching RC5-Keys with Distributed Reconfigurable Computing.
Proceedings of the 2006 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2006

Symbolic Archive Representation for a Fast Nondominance Test.
Proceedings of the Evolutionary Multi-Criterion Optimization, 4th International Conference, 2006

Task-accurate performance modeling in SystemC for real-time multi-processor architectures.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Bridging the Gap between Relocatability and Available Technology: The Erlangen Slot Machine.
Proceedings of the Dynamically Reconfigurable Architectures, 02.04. - 07.04.2006, 2006

06141 Abstracts Collection -- Dynamically Reconfigurable Architectures.
Proceedings of the Dynamically Reconfigurable Architectures, 02.04. - 07.04.2006, 2006

06141 Executive Summary -- Dynamically Reconfigurable Architectures.
Proceedings of the Dynamically Reconfigurable Architectures, 02.04. - 07.04.2006, 2006

Are current ESL tools meeting the requirements of advanced embedded systems?
Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, 2006

A Generic Framework for Rapid Prototyping of System-on-Chip Designs.
Proceedings of the 2006 International Conference on Computer Design & Conference on Computing in Nanotechnology, 2006

A Design Methodology for Hardware Acceleration of Adaptive Filter Algorithms in Image Processing.
Proceedings of the 2006 IEEE International Conference on Application-Specific Systems, 2006

A Flexible Reconfiguration Manager for the Erlangen Slot Machine.
Proceedings of the ARCS 2006, 2006

An Operating System Infrastructure for Fault-Tolerant Reconfigurable Networks.
Proceedings of the Architecture of Computing Systems, 2006

Controller Synthesis for Mapping Partitioned Programs on Array Architectures.
Proceedings of the Architecture of Computing Systems, 2006

2005
Online placement for dynamically reconfigurable devices.
IJES, 2005

Automatic FIR Filter Generation for FPGAs.
Proceedings of the Embedded Computer Systems: Architectures, 2005

A Practical Approach for Circuit Routing on Dynamic Reconfigurable Devices.
Proceedings of the 16th IEEE International Workshop on Rapid System Prototyping (RSP 2005), 2005

Co-Design of Massively Parallel Embedded Processor Architectures.
Proceedings of the 1st International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2005

Packet Routing in Dynamically Changing Networks on Chip.
Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005

SPI-Workbench - Modellierung, Analyse und Optimierung eingebetteter Systeme.
Proceedings of the INFORMATIK 2005, 2005

Improving EA-based design space exploration by utilizing symbolic feasibility tests.
Proceedings of the Genetic and Evolutionary Computation Conference, 2005

The Erlangen Slot Machine: Increasing Flexibility in FPGA-Based Reconfigurable Platforms.
Proceedings of the 2005 IEEE International Conference on Field-Programmable Technology, 2005

DyNoC: A Dynamic Infrastructure for Communication in Dynamically Reconfigurable Devices.
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

The Erlangen Slot Machine: A Highly Flexible FPGA-Based Reconfigurable Platform.
Proceedings of the 13th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2005), 2005

Defragmenting the Module Layout of a Partially Reconfigurable Device.
Proceedings of The 2005 International Conference on Engineering of Reconfigurable Systems and Algorithms, 2005

Output Serialization for FPGA-based and Coarse-grained Processor Arrays.
Proceedings of The 2005 International Conference on Engineering of Reconfigurable Systems and Algorithms, 2005

Initial Population Construction for Convergence Improvement of MOEAs.
Proceedings of the Evolutionary Multi-Criterion Optimization, 2005

Distributed HW/SW-Partitioning for Embedded Reconfigurable Networks.
Proceedings of the 2005 Design, 2005

A New Approach on Many Objective Diversity Measurement.
Proceedings of the Practical Approaches to Multi-Objective Optimization, 2005

Modeling and analysis of indirect communication in particle swarm optimization.
Proceedings of the IEEE Congress on Evolutionary Computation, 2005

Online hardware/software partitioning in networked embedded systems.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

A system-level approach to hardware reconfigurable systems.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Using Symbolic Feasibility Tests during Design Space Exploration of Heterogeneous Multi-Processor Systems.
Proceedings of the 16th IEEE International Conference on Application-Specific Systems, 2005

Quad-trees: A Data Structure for Storing Pareto Sets in Multiobjective Evolutionary Algorithms with Elitism.
Proceedings of the Evolutionary Multiobjective Optimization, 2005

2004
Systematic integration of parameterized local search into evolutionary algorithms.
IEEE Trans. Evolutionary Computation, 2004

Task scheduling for heterogeneous reconfigurable computers.
Proceedings of the 17th Annual Symposium on Integrated Circuits and Systems Design, 2004

Analysis of Dataflow Programs with Interval-Limited Data-Rates.
Proceedings of the Computer Systems: Architectures, 2004

High-Speed Event-Driven RTL Compiled Simulation.
Proceedings of the Computer Systems: Architectures, 2004

Basic OS Support for Distributed Reconfigurable Hardware.
Proceedings of the Computer Systems: Architectures, 2004

Dynamic Piecewise Linear/Regular Algorithms.
Proceedings of the 2004 International Conference on Parallel Computing in Electrical Engineering (PARELEC 2004), 2004

Mapping of Regular Nested Loop Programs to Coarse-Grained Reconfigurable Arrays - Constraints and Methodology.
Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), 2004

Real-Time Configuration Code Decompression for Dynamic FPGA Self-Reconfiguration.
Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), 2004

A New Approach for On-line Placement on Reconfigurable Devices.
Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), 2004

Regular mapping for coarse-grained reconfigurable architectures.
Proceedings of the 2004 IEEE International Conference on Acoustics, 2004

Systematic Integration of Parameterized Local Search Techniques in Evolutionary Algorithms.
Proceedings of the Genetic and Evolutionary Computation, 2004

A Dynamic NoC Approach for Communication in Reconfigurable Devices.
Proceedings of the Field Programmable Logic and Application, 2004

Optimal Routing-Conscious Dynamic Placement for Reconfigurable Devices.
Proceedings of the Field Programmable Logic and Application, 2004

Platform-independent methodology for partial reconfiguration.
Proceedings of the First Conference on Computing Frontiers, 2004

Covering Pareto-optimal fronts by subswarms in multi-objective particle swarm optimization.
Proceedings of the IEEE Congress on Evolutionary Computation, 2004

Molecular force field parametrization using multi-objective evolutionary algorithms.
Proceedings of the IEEE Congress on Evolutionary Computation, 2004

Resource Constrained and Speculative Scheduling of an Algorithm Class with Run-Time Dependent Conditionals.
Proceedings of the 15th IEEE International Conference on Application-Specific Systems, 2004

Generation of Distributed Arithmetic Designs for Reconfigurable Application.
Proceedings of the ARCS 2004, 2004

A Dynamic Scheduling and Placement Algorithm for Reconfigurable Hardware.
Proceedings of the Organic and Pervasive Computing, 2004

2003
Automatic Synthesis of FPGA Processor Arrays from Loop Algorithms.
The Journal of Supercomputing, 2003

BUILDABONG: A Framework for Architecture/Compiler Co-Exploration for ASIPs.
Journal of Circuits, Systems, and Computers, 2003

Design and Implementation of Digital Linear Control Systems on Reconfigurable Hardware.
EURASIP J. Adv. Sig. Proc., 2003

Speeding up Online Placement for XILINX FPGAs by Reducing Configuration Overhead.
Proceedings of the IFIP VLSI-SoC 2003, 2003

Strategies for finding good local guides in multi-objective particle swarm optimization (MOPSO).
Proceedings of the 2003 IEEE Swarm Intelligence Symposium, 2003

ReCoNet: Modeling and Implementation of Fault Tolerant Distributed Reconfigurable Hardware.
Proceedings of the 16th Annual Symposium on Integrated Circuits and Systems Design, 2003

FPGA designs of parallel high performance GF(2233) multipliers.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

A High Performance VLIW Processor for Finite Field Arithmetic.
Proceedings of the 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 2003

A new approach for reconfigurable massively parallel computers.
Proceedings of the 2003 IEEE International Conference on Field-Programmable Technology, 2003

Temporal task clustering for online placement on reconfigurable hardware.
Proceedings of the 2003 IEEE International Conference on Field-Programmable Technology, 2003

Fault Tolerances Analysis of Distributed Reconfigurable Systems Using SAT-Based Techniques.
Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003

Covering Pareto Sets by Multilevel Evolutionary Subdivision Techniques.
Proceedings of the Evolutionary Multi-Criterion Optimization, 2003

Solving Hierarchical Optimization Problems Using MOEAs.
Proceedings of the Evolutionary Multi-Criterion Optimization, 2003

SAT-Based Techniques in System Synthesis.
Proceedings of the 2003 Design, 2003

Improved Time Domain Simulation of Optical Multimode Intrasystem Interconnects.
Proceedings of the 2003 Design, 2003

Accelerating design space exploration using pareto-front arithmetics.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002
SPI - a system model for heterogeneously specified embedded systems.
IEEE Trans. VLSI Syst., 2002

Energy estimation of nested loop programs.
Proceedings of the Fourteenth Annual ACM Symposium on Parallel Algorithms and Architectures, 2002

Exact Partitioning of Affine Dependence Algorithms.
Proceedings of the Embedded Processor Design Challenges: Systems, Architectures, Modeling, and Simulation, 2002

Flexibility/Cost-Tradeoffs of Platform-Based Systems.
Proceedings of the Embedded Processor Design Challenges: Systems, Architectures, Modeling, and Simulation, 2002

Generation of Distributed Loop Control.
Proceedings of the Embedded Processor Design Challenges: Systems, Architectures, Modeling, and Simulation, 2002

Modellierung rekonfigurierbarer Systemarchitekturen.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2002

Tradeoff analysis of FPGA based elliptic curve cryptography.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Reconfigurable Implementation of Elliptic Curve Crypto Algorithms.
Proceedings of the 16th International Parallel and Distributed Processing Symposium (IPDPS 2002), 2002

(Self-)reconfigurable Finite State Machines: Theory and Implementation.
Proceedings of the 2002 Design, 2002

System Design for Flexibility.
Proceedings of the 2002 Design, 2002

Efficient architecture/compiler co-exploration for ASIPs.
Proceedings of the International Conference on Compilers, 2002

2001
FunState-an internal design representation for codesign.
IEEE Trans. VLSI Syst., 2001

Optimization of Dynamic Hardware Reconfigurations.
The Journal of Supercomputing, 2001

Extending Partial Suborders.
Electronic Notes in Discrete Mathematics, 2001

Higher-Dimensional Packing with Order Constraints.
Proceedings of the Algorithms and Data Structures, 7th International Workshop, 2001

Design Space Exploration for Massively Parallel Processor Arrays.
Proceedings of the Parallel Computing Technologies, 2001

Pareto-Front Exploration with Uncertain Objectives.
Proceedings of the Evolutionary Multi-Criterion Optimization, 2001

Optimal FPGA module placement with temporal precedence constraints.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

Hybrid global/local search strategies for dynamic voltage scaling in embedded multiprocessors.
Proceedings of the Ninth International Symposium on Hardware/Software Codesign, 2001

Design space characterization for architecture/compiler co-exploration.
Proceedings of the 2001 International Conference on Compilers, 2001

2000
Multidimensional Exploration of Software Implementations for DSP Algorithms.
VLSI Signal Processing, 2000

Evolutionary algorithms for the synthesis of embedded software.
IEEE Trans. VLSI Syst., 2000

Regular state machines.
Parallel Algorithms Appl., 2000

EXPLORA - Generic Design Space Exploration during Embedded System Synthesis.
Proceedings of the Architecture and Design of Distributed Embedded Systems, 2000

A joined architecture/compiler design environment for ASIPs.
Proceedings of the 2000 International Conference on Compilers, 2000

Description and Simulation of Microprocessor Instruction Sets Using ASMs.
Proceedings of the Abstract State Machines, 2000

Tradeoff Analysis and Architecture Design of a Hybrid Hardware/Software Sorter.
Proceedings of the 12th IEEE International Conference on Application-Specific Systems, 2000

1999
Compile-time Optimization of Dynamic Hardware Reconfigurations.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 1999

SPI -- An Internal Representation for Heterogeneously Specified Embedded Systems.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 1999

FunState - an internal design representation for codesign.
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

Representation of Function Variants for Embedded System Optimization and Synthesis.
Proceedings of the 36th Conference on Design Automation, 1999

3D exploration of software schedules for DSP algorithms.
Proceedings of the Seventh International Workshop on Hardware/Software Codesign, 1999

Scheduling hardware/software systems using symbolic techniques.
Proceedings of the Seventh International Workshop on Hardware/Software Codesign, 1999

1998
System-Level Synthesis Using Evolutionary Algorithms.
Design Autom. for Emb. Sys., 1998

Buffer Memory Optimization in DSP Applications - An Evolutionary Approach.
Proceedings of the Parallel Problem Solving from Nature, 1998

Representation of process mode correlation for scheduling.
Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

Rapid Prototyping of Dataflow Programs on Hardware/Software Architectures.
Proceedings of the Thirty-First Annual Hawaii International Conference on System Sciences, 1998

Interfacing Hardware and Software.
Proceedings of the Field-Programmable Logic and Applications, 1998

Combining multiple models of computation for scheduling and allocation.
Proceedings of the Sixth International Workshop on Hardware/Software Codesign, 1998

Domain-specific interface generation from dataflow specifications.
Proceedings of the Sixth International Workshop on Hardware/Software Codesign, 1998

1997
Partitioning Processor Arrays under Resource Constraints.
VLSI Signal Processing, 1997

Performance analysis and optimization of mixed asynchronous synchronous systems.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1997

An evolutionary approach to system-level synthesis.
Proceedings of the Fifth International Workshop on Hardware/Software Codesign, 1997

Digitale Hardware/Software-Systeme - Synthese und Optimierung.
Springer, ISBN: 978-3-540-62433-2, 1997

1996
Scheduling of Partitioned Regular Algorithms on Processor Arrays with Constrained Resources.
Proceedings of the 1996 International Conference on Application-Specific Systems, 1996

1995
Modeling and simulation of heterogeneous real-time systems based on a deterministic discrete event model.
Proceedings of the 8th International Symposium on System Synthesis (ISSS 1995), 1995

Minimal Enclosing Parallelogram with Application.
Proceedings of the Eleventh Annual Symposium on Computational Geometry, 1995

1993
A compiler for application specific processor arrays.
PhD thesis, 1993

Partitioning of processor arrays: a piecewise regular approach.
Integration, 1993

1991
Control generation in the design of processor arrays.
VLSI Signal Processing, 1991


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