Vaibhav Venugopal Rao

Orcid: 0000-0002-9369-1730

According to our database1, Vaibhav Venugopal Rao authored at least 10 papers between 2017 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
Hidden Costs of Analog Deobfuscation Attacks.
IEEE Trans. Very Large Scale Integr. Syst., November, 2023

2022
Analysis of the Security Vulnerabilities of 2.5-D and 3-D Integrated Circuits.
Proceedings of the 23rd International Symposium on Quality Electronic Design, 2022

Practical Performance of Analog Attack Techniques.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2022

2021
Performance and Security Analysis of Parameter-Obfuscated Analog Circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2021

2020
Security Vulnerabilities of Obfuscated Analog Circuits.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2019
Mesh Based Obfuscation of Analog Circuit Properties.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Securing Analog Mixed-Signal Integrated Circuits Through Shared Dependencies.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

2018
Transistor Sizing for Parameter Obfuscation of Analog Circuits Using Satisfiability Modulo Theory.
Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018

2017
Protecting analog circuits with parameter biasing obfuscation.
Proceedings of the 18th IEEE Latin American Test Symposium, 2017

Parameter biasing obfuscation for analog IP protection.
Proceedings of the 2017 IEEE International Symposium on Hardware Oriented Security and Trust, 2017


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