Kyle Juretus

According to our database, Kyle Juretus authored at least 19 papers between 2016 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2023

Hidden Costs of Analog Deobfuscation Attacks.

Vaibhav Venugopal Rao, Kyle Juretus, Ioannis Savidis

IEEE Trans. Very Large Scale Integr. Syst., November, 2023

Deep Learning Sparse Array Design Using Binary Switching Configurations.

Syed A. Hamza, Kyle Juretus, Moeness G. Amin, Fauzia Ahmad

Proceedings of the IEEE International Conference on Acoustics, 2023

2022

Lightweight Hardware Implementation of Binary Ring-LWE PQC Accelerator.

Benjamin J. Lucas, Ali Alwan, Marion Murzello, Yazheng Tu, Pengzhou He, Andrew J. Schwartz, David Guevara, Ujjwal Guin, Kyle Juretus, Jiafeng Xie

IEEE Comput. Archit. Lett., 2022

Practical Performance of Analog Attack Techniques.

Vaibhav Venugopal Rao, Kyle Juretus, Ioannis Savidis

Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2022

2021

Increased Output Corruption and Structural Attack Resilience for SAT Attack Secure Logic Locking.

Kyle Juretus, Ioannis Savidis

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

Synthesis of Hidden State Transitions for Sequential Logic Locking.

Kyle Juretus, Ioannis Savidis

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

2020

Characterization of In-Cone Logic Locking Resiliency Against the SAT Attack.

Kyle Juretus, Ioannis Savidis

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Physical Layer Encryption for Wireless OFDM Communication Systems.

Marko Jacovic, Kyle Juretus, Nagarajan Kandasamy, Ioannis Savidis, Kapil R. Dandekar

J. Hardw. Syst. Secur., 2020

Security Vulnerabilities of Obfuscated Analog Circuits.

Vaibhav Venugopal Rao, Kyle Juretus, Ioannis Savidis

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Reducing Logic Locking Key Leakage through the Scan Chain.

Kyle Juretus, Ioannis Savidis

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2019

Securing Wireless Communication via Hardware-Based Packet Obfuscation.

James Chacko, Kyle Juretus, Marko Jacovic, Cem Sahin, Nagarajan Kandasamy, Ioannis Savidis, Kapil R. Dandekar

J. Hardw. Syst. Secur., 2019

Increasing the SAT Attack Resiliency of In-Cone Logic Locking.

Kyle Juretus, Ioannis Savidis

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Securing Analog Mixed-Signal Integrated Circuits Through Shared Dependencies.

Kyle Juretus, Vaibhav Venugopal Rao, Ioannis Savidis

Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

2018

Time Domain Sequential Locking for Increased Security.

Kyle Juretus, Ioannis Savidis

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Machine Learning on the Thermal Side-Channel: Analysis of Accelerator-Rich Architectures.

David Werner, Kyle Juretus, Ioannis Savidis, Mark Hempstead

Proceedings of the 36th IEEE International Conference on Computer Design, 2018

Importance of Multi-parameter SAT Attack Exploration for Integrated Circuit Security.

Kyle Juretus, Ioannis Savidis

Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018

2017

Physical gate based preamble obfuscation for securing wireless communication.

James Chacko, Kyle Juretus, Marko Jacovic, Cem Sahin, Nagarajan Kandasamy, Ioannis Savidis, Kapil R. Dandekar

Proceedings of the 2017 International Conference on Computing, 2017

2016

Reducing logic encryption overhead through gate level key insertion.

Kyle Juretus, Ioannis Savidis

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Reduced Overhead Gate Level Logic Encryption.

Kyle Juretus, Ioannis Savidis

Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016