Avesta Sasan
Orcid: 0000-0002-4052-8075Affiliations:
- George Mason University, Fairfax, VA, USA
According to our database1,
Avesta Sasan
authored at least 117 papers
between 2006 and 2023.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
Online presence:
-
on orcid.org
-
on dl.acm.org
On csauthors.net:
Bibliography
2023
ACM Trans. Embed. Comput. Syst., 2023
HW-V2W-Map: Hardware Vulnerability to Weakness Mapping Framework for Root Cause Analysis with GPT-assisted Mitigation Suggestion.
CoRR, 2023
Advanced Reinforcement Learning Solution for Clock Skew Engineering: Modified Q-Table Update Technique for Peak Current and IR Drop Minimization.
IEEE Access, 2023
Securing AI Hardware: Challenges in Detecting and Mitigating Hardware Trojans in ML Accelerators.
Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023
Gotcha! I Know What You Are Doing on the FPGA Cloud: Fingerprinting Co-Located Cloud FPGA Accelerators via Measuring Communication Links.
Proceedings of the 2023 ACM SIGSAC Conference on Computer and Communications Security, 2023
2022
ACM Trans. Design Autom. Electr. Syst., 2022
Proceedings of the 20th IEEE Interregional NEWCAS Conference, 2022
Proceedings of the 29th Annual Network and Distributed System Security Symposium, 2022
Proceedings of the 23rd International Symposium on Quality Electronic Design, 2022
Proceedings of the 23rd International Symposium on Quality Electronic Design, 2022
CAD-FSL: Code-Aware Data Generation based Few-Shot Learning for Efficient Malware Detection.
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022
RAPTA: A Hierarchical Representation Learning Solution For Real-Time Prediction of Path-Based Static Timing Analysis.
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022
LOCK&ROLL: deep-learning power side-channel attack mitigation using emerging reconfigurable devices and logic locking.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022
2021
IEEE Trans. Very Large Scale Integr. Syst., 2021
Adaptive Performance Modeling of Data-intensive Workloads for Resource Provisioning in Virtualized Environment.
ACM Trans. Model. Perform. Evaluation Comput. Syst., 2021
CPM: A general feature dependency pattern mining framework for contrast multivariate time series.
Pattern Recognit., 2021
IEEE J. Emerg. Sel. Topics Circuits Syst., 2021
AVATAR: NN-Assisted Variation Aware Timing Analysis and Reporting for Hardware Trojan Detection.
IEEE Access, 2021
From Cryptography to Logic Locking: A Survey on the Architecture Evolution of Secure Scan Chains.
IEEE Access, 2021
Cloak & Co-locate: Adversarial Railroading of Resource Sharing-based Attacks on the Cloud.
Proceedings of the 2021 International Symposium on Secure and Private Execution Environment Design (SEED), 2021
Machine Learning-Assisted Website Fingerprinting Attacks with Side-Channel Information: A Comprehensive Analysis and Characterization.
Proceedings of the 22nd International Symposium on Quality Electronic Design, 2021
Proceedings of the 22nd International Symposium on Quality Electronic Design, 2021
Diverse Knowledge Distillation (DKD): A Solution for Improving The Robustness of Ensemble Models Against Adversarial Attacks.
Proceedings of the 22nd International Symposium on Quality Electronic Design, 2021
Proceedings of the 22nd International Symposium on Quality Electronic Design, 2021
RANE: An Open-Source Formal De-obfuscation Attack for Reverse Engineering of Logic Encrypted Circuits.
Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021
Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021
Energy-Efficient and Adversarially Robust Machine Learning with Selective Dynamic Band Filtering.
Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021
A Reinforced Learning Solution for Clock Skew Engineering to Reduce Peak Current and IR Drop.
Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021
Securing Hardware via Dynamic Obfuscation Utilizing Reconfigurable Interconnect and Logic Blocks.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021
Evaluation of Machine Learning-based Detection against Side-Channel Attacks on Autonomous Vehicle.
Proceedings of the 3rd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2021
2020
SAT-Hard Cyclic Logic Obfuscation for Protecting the IP in the Manufacturing Supply Chain.
IEEE Trans. Very Large Scale Integr. Syst., 2020
ACM Trans. Embed. Comput. Syst., 2020
Cluster-Based Partitioning of Convolutional Neural Networks, A Solution for Computational Energy and Complexity Reduction.
CoRR, 2020
Learning Diverse Latent Representations for Improving the Resilience to Adversarial Attacks.
CoRR, 2020
CoRR, 2020
Cognitive and Scalable Technique for Securing IoT Networks Against Malware Epidemics.
IEEE Access, 2020
DFSSD: Deep Faults and Shallow State Duality, A Provably Strong Obfuscation Solution for Circuits with Restricted Access to Scan Chain.
Proceedings of the 38th IEEE VLSI Test Symposium, 2020
SCRAMBLE: The State, Connectivity and Routing Augmentation Model for Building Logic Encryption.
Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020
Proceedings of the 21st International Symposium on Quality Electronic Design, 2020
Proceedings of the 21st International Symposium on Quality Electronic Design, 2020
Code-Bridged Classifier (CBC): A Low or Negative Overhead Defense for Making a CNN Classifier Robust Against Adversarial Attacks.
Proceedings of the 21st International Symposium on Quality Electronic Design, 2020
SCARF: Detecting Side-Channel Attacks at Real-time using Low-level Hardware Features.
Proceedings of the 26th IEEE International Symposium on On-Line Testing and Robust System Design, 2020
HybriDG: Hybrid Dynamic Time Warping and Gaussian Distribution Model for Detecting Emerging Zero-Day Microarchitectural Side-Channel Attacks.
Proceedings of the 19th IEEE International Conference on Machine Learning and Applications, 2020
Phased-Guard: Multi-Phase Machine Learning Framework for Detection and Identification of Zero-Day Microarchitectural Side-Channel Attacks.
Proceedings of the 38th IEEE International Conference on Computer Design, 2020
Hybrid-Shield: Accurate and Efficient Cross-Layer Countermeasure for Run-Time Detection and Mitigation of Cache-Based Side-Channel Attacks.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020
Comprehensive Evaluation of Machine Learning Countermeasures for Detecting Microarchitectural Side-Channel Attacks.
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020
StealthMiner: Specialized Time Series Machine Learning for Run-Time Stealthy Malware Detection based on Microarchitectural Features.
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020
Mitigating Cache-Based Side-Channel Attacks through Randomization: A Comprehensive System and Architecture Level Analysis.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020
2019
SMT Attack: Next Generation Attack on Obfuscated Circuits with Capabilities and Performance Beyond the SAT Attacks.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2019
Pyramid: Machine Learning Framework to Estimate the Optimal Timing and Resource Usage of a High-Level Synthesis Design.
CoRR, 2019
TCD-NPE: A Re-configurable and Efficient Neural Processing Engine, Powered by Novel Temporal-Carry-deferring MACs.
Proceedings of the 2019 International Conference on ReConFigurable Computing and FPGAs, 2019
Proceedings of the 22nd International Symposium on Research in Attacks, 2019
Exploiting Energy-Accuracy Trade-off through Contextual Awareness in Multi-Stage Convolutional Neural Networks.
Proceedings of the 20th International Symposium on Quality Electronic Design, 2019
Proceedings of the 48th International Conference on Parallel Processing, 2019
Security and Complexity Analysis of LUT-based Obfuscation: From Blueprint to Reality.
Proceedings of the International Conference on Computer-Aided Design, 2019
Mitigating the Performance and Quality of Parallelized Compressive Sensing Reconstruction Using Image Stitching.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019
2SMaRT: A Two-Stage Machine Learning-Based Approach for Run-Time Specialized Hardware-Assisted Malware Detection.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
Full-Lock: Hard Distributions of SAT instances for Obfuscating Circuits using Fully Configurable Logic and Routing Blocks.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
IR-ATA: IR annotated timing analysis, a flow for closing the loop between PDN design, IR analysis & timing closure.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019
XPPE: cross-platform performance estimation of hardware accelerators using machine learning.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019
2018
IEEE Trans. Multi Scale Comput. Syst., 2018
J. Parallel Distributed Comput., 2018
Architectural considerations for FPGA acceleration of machine learning applications in MapReduce.
Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, 2018
LUT-Lock: A Novel LUT-Based Logic Obfuscation for FPGA-Bitstream and ASIC-Hardware Protection.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018
Benchmarking the Capabilities and Limitations of SAT Solvers in Defeating Obfuscation Schemes.
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018
MUCH-SWIFT: A High-Throughput Multi-Core HW/SW Co-design K-means Clustering Architecture.
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018
Design Space Exploration for Hardware Acceleration of Machine Learning Applications in MapReduce.
Proceedings of the 26th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2018
ICNN: An iterative implementation of convolutional neural networks to enable energy and computational complexity aware dynamic approximation.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
Ensemble learning for effective run-time hardware-based malware detection: a comprehensive analysis and classification.
Proceedings of the 55th Annual Design Automation Conference, 2018
Proceedings of the International Conference on Compilers, 2018
2017
A Power Delivery Network and Cell Placement Aware IR-Drop Mitigation Technique: Harvesting Unused Timing Slacks to Schedule Useful Skews.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017
Spatial and temporal scheduling of clock arrival times for IR hot-spot mitigation, reformulation of peak current reduction.
Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017
Machine Learning-Based Approaches for Energy-Efficiency Prediction and Scheduling in Composite Cores Architectures.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
Proceedings of the 54th Annual Design Automation Conference, 2017
2016
Characterizing Hadoop applications on microservers for performance and energy efficiency optimizations.
Proceedings of the 2016 IEEE International Symposium on Performance Analysis of Systems and Software, 2016
Big biomedical image processing hardware acceleration: A case study for K-means and image filtering.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Proceedings of the Eleventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2016
Erratum to: Chapter 4 Resizable Data Composer (RDC) Cache: A Near-Threshold Cache Tolerating Process Variation via Architectural Fault Tolerance.
Proceedings of the Near Threshold Computing, Technology, Methods and Applications., 2016
Resizable Data Composer (RDC) Cache: A Near-Threshold Cache Tolerating Process Variation via Architectural Fault Tolerance.
Proceedings of the Near Threshold Computing, Technology, Methods and Applications., 2016
2015
Proceedings of the 2015 IEEE International Conference on Big Data (IEEE BigData 2015), Santa Clara, CA, USA, October 29, 2015
System and architecture level characterization of big data applications on big and little core server architectures.
Proceedings of the 2015 IEEE International Conference on Big Data (IEEE BigData 2015), Santa Clara, CA, USA, October 29, 2015
2012
Variation Trained Drowsy Cache (VTD-Cache): A History Trained Variation Aware Drowsy Cache for Fine Grain Voltage Scaling.
IEEE Trans. Very Large Scale Integr. Syst., 2012
History & Variation Trained Cache (HVT-Cache): A process variation aware and fine grain voltage scalable cache with active access history monitoring.
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012
2011
Inquisitive Defect Cache: A Means of Combating Manufacturing Induced Process Variation.
IEEE Trans. Very Large Scale Integr. Syst., 2011
MZZ-HVS: Multiple Sleep Modes Zig-Zag Horizontal and Vertical Sleep Transistor Sharing to Reduce Leakage Power in On-Chip SRAM Peripheral Circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2011
Reducing Power in All Major CAM and SRAM-Based Processor Units via Centralized, Dynamic Resource Size Management.
IEEE Trans. Very Large Scale Integr. Syst., 2011
2010
RELOCATE: Register File Local Access Pattern Redistribution Mechanism for Power and Thermal Management in Out-of-Order Embedded Processor.
Proceedings of the High Performance Embedded Architectures and Compilers, 2010
Multiple sleep modes leakage control in peripheral circuits of a all major SRAM-based processor units.
Proceedings of the 7th Conference on Computing Frontiers, 2010
2009
IEEE Trans. Very Large Scale Integr. Syst., 2009
Proceedings of the 1st International Conference on Intelligent Networking and Collaborative Systems, 2009
Proceedings of the Design, Automation and Test in Europe, 2009
A fault tolerant cache architecture for sub 500mV operation: resizable data composer cache (RDC-cache).
Proceedings of the 2009 International Conference on Compilers, 2009
2008
Architectural and algorithm level fault tolerant techniques for low power high yield multimedia devices.
Proceedings of the 2008 International Conference on Embedded Computer Systems: Architectures, 2008
Proceedings of the 2008 International Conference on Embedded Computer Systems: Architectures, 2008
Improving performance and reducing energy-delay with adaptive resource resizing for out-of-order embedded processors.
Proceedings of the 2008 ACM SIGPLAN/SIGBED Conference on Languages, 2008
ZZ-HVS: Zig-zag horizontal and vertical sleep transistor sharing to reduce leakage power in on-chip SRAM peripheral circuits.
Proceedings of the 26th International Conference on Computer Design, 2008
Dynamic register file resizing and frequency scaling to improve embedded processor performance and energy-delay efficiency.
Proceedings of the 45th Design Automation Conference, 2008
Multiple sleep mode leakage control for cache peripheral circuits in embedded processors.
Proceedings of the 2008 International Conference on Compilers, 2008
2007
Proceedings of the 25th International Conference on Computer Design, 2007
Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007
2006
Proceedings of the Eighth IEEE International Conference on E-Commerce Technology (CEC 2006) / Third IEEE International Conference on Enterprise Computing, 2006