Venkata Sreekanth Balijabudda

According to our database, Venkata Sreekanth Balijabudda authored at least 4 papers between 2019 and 2025.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2025

PUFBind: PUF-Enabled Lightweight Program Binary Authentication for FPGA-based Embedded Systems.

Sneha Swaroopa, Venkata Sreekanth Balijabudda, Rajat Subhra Chakraborty, Indrajit Chakrabarti

CoRR, January, 2025

2024

Design, Implementation and Characterization of a Novel Robust-by-Construction Arbiter PUF Circuit on Xilinx FPGAs.

Venkata Sreekanth Balijabudda, Indrajit Chakrabarti, Rajat Subhra Chakraborty

Proceedings of the 33rd IEEE Asian Test Symposium, 2024

2023

Theoretical Enumeration of Deployable Single-Output Strong PUF Instances Based on Uniformity and Uniqueness Constraints.

Venkata Sreekanth Balijabudda, Kamalesh Acharya, Rajat Subhra Chakraborty, Indrajit Chakrabarti

Proceedings of the Information Systems Security - 19th International Conference, 2023

2019

Design of a Chaotic Oscillator based Model Building Attack Resistant Arbiter PUF.

Venkata Sreekanth Balijabudda, Dhruv Thapar, Pranesh Santikellur, Rajat Subhra Chakraborty, Indrajit Chakrabarti

Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2019