Dhruv Thapar

Orcid: 0009-0001-1050-0960

According to our database1, Dhruv Thapar authored at least 17 papers between 2019 and 2026.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

On csauthors.net:

Bibliography

2026
Modeling and Analysis of Defects and Variations in Multibit FeFET Devices and Crossbar Architectures.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., February, 2026

WARP-TPG: Warpage-Aware Test Pattern Generation for Small-Delay Defects.
Proceedings of the 44th IEEE VLSI Test Symposium, 2026

NERT: Network- and Routing-aware Testing of Interconnects in Fanout Wafer-Level Packaging.
Proceedings of the 44th IEEE VLSI Test Symposium, 2026

WARP: Workload-Aware Reference Prediction for Reliable Multi-Bit FeFET Readout under Charge-Trapping Degradation.
Proceedings of the 31st Asia and South Pacific Design Automation Conference, 2026

2025
SPICED+: Syntactical Bug Pattern Identification and Correction of Trojans in A/MS Circuits Using LLM-Enhanced Detection.
IEEE Trans. Very Large Scale Integr. Syst., April, 2025

FeTest: Defect Analysis and March Test Solution for FeFETs <sup>*</sup>.
Proceedings of the IEEE International Test Conference, 2025

NeuralTPG: GPU-Accelerated Neural Twin-Based Test Pattern Generation for Transition Delay Faults in Safety-Critical Applications.
Proceedings of the IEEE International Test Conference, 2025

SMART: Scalable and Modular Architecture for Routing-Aware Testing of Fan-out Wafer-Level Packages<sup>*</sup>.
Proceedings of the IEEE International Test Conference, 2025

On the Impact of Warpage on BEOL Geometry and Path Delays in Fan-out Wafer-Level Packaging.
Proceedings of the Design, Automation & Test in Europe Conference, 2025

2024
SPICED: Syntactical Bug and Trojan Pattern Identification in A/MS Circuits using LLM-Enhanced Detection.
CoRR, 2024

Defect Analysis for FeFETs using a Compact Model.
Proceedings of the IEEE International Test Conference, 2024

Safety-Guided Test Generation for Structural Faults.
Proceedings of the IEEE International Test Conference, 2024

2023
Analysis and Characterization of Defects in FeFETs.
Proceedings of the IEEE International Test Conference, 2023

2021
Deep Learning assisted Cross-Family Profiled Side-Channel Attacks using Transfer Learning.
Proceedings of the 22nd International Symposium on Quality Electronic Design, 2021

2020
TranSCA: Cross-Family Profiled Side-Channel Attacks using Transfer Learning on Deep Neural Networks.
IACR Cryptol. ePrint Arch., 2020

2019
Adaptive Multi-bit SRAM Topology Based Analog PUF.
CoRR, 2019

Design of a Chaotic Oscillator based Model Building Attack Resistant Arbiter PUF.
Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2019


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