Viacheslav V. Fedorov

According to our database, Viacheslav V. Fedorov authored at least 7 papers between 2013 and 2021.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2021

Hardware Acceleration of Hash Operations in Modern Microprocessors.

Abbas A. Fairouz, Monther Abusultan, Viacheslav V. Fedorov, Sunil P. Khatri

IEEE Trans. Computers, 2021

2017

Speculative paging for future NVM storage.

Viacheslav V. Fedorov, Jinchun Kim, Mian Qin, Paul V. Gratz, A. L. Narasimha Reddy

Proceedings of the International Symposium on Memory Systems, 2017

2016

FTCAM: An Area-Efficient Flash-Based Ternary CAM Design.

Viacheslav V. Fedorov, Monther Abusultan, Sunil P. Khatri

IEEE Trans. Computers, 2016

2015

Dynamic Memory Pressure Aware Ballooning.

Jinchun Kim, Viacheslav V. Fedorov, Paul V. Gratz, A. L. Narasimha Reddy

Proceedings of the 2015 International Symposium on Memory Systems, 2015

Shared Last-Level Caches and The Case for Longer Timeslices.

Viacheslav V. Fedorov, A. L. Narasimha Reddy, Paul V. Gratz

Proceedings of the 2015 International Symposium on Memory Systems, 2015

2014

An area-efficient Ternary CAM design using floating gate transistors.

Viacheslav V. Fedorov, Monther Abusultan, Sunil P. Khatri

Proceedings of the 32nd IEEE International Conference on Computer Design, 2014

2013

ARI: Adaptive LLC-memory traffic management.

Viacheslav V. Fedorov, Sheng Qiu, A. L. Narasimha Reddy, Paul V. Gratz

ACM Trans. Archit. Code Optim., 2013