Victor Avendaño

According to our database, Victor Avendaño authored at least 6 papers between 2001 and 2015.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2015

A controllable setup and propagation delay flip-flop design.

Alexandro Giron-Allende, Victor Avendaño, Esteban Martinez Guerrero

Proceedings of the 16th Latin-American Test Symposium, 2015

A design methodology using flip-flops controlled by PVT variation detection.

Alexandro Giron-Allende, Victor Avendaño, Esteban Martinez Guerrero

Proceedings of the IEEE 6th Latin American Symposium on Circuits & Systems, 2015

2010

Built-In Sensor for Signal Integrity Faults in Digital Interconnect Signals.

Víctor H. Champac, Victor Avendaño, Joan Figueras

IEEE Trans. Very Large Scale Integr. Syst., 2010

2004

Signal integrity verification using high speed monitors.

Victor Avendaño, Víctor H. Champac, Joan Figueras

Proceedings of the 9th European Test Symposium, 2004

2003

Signal integrity loss in bus lines due to open shielding defects.

Victor Avendaño, Víctor H. Champac, Joan Figueras

Proceedings of the 8th European Test Workshop, 2003

2001

Test of Data Retention Faults Sensing the Bit Line with a DFT Bases Differential Amplifier.

Víctor H. Champac, Victor Avendaño, Gordana Jovanovic-Dolecek

Proceedings of the 2nd Latin American Test Workshop, 2001