Joan Figueras

According to our database, Joan Figueras authored at least 124 papers between 1991 and 2020.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2020

Indirect and adaptive test of analogue circuits based on preselected steady-state response measures.

Álvaro Gómez-Pau, Emili Lupon, Luz Balado, Joan Figueras

IET Circuits Devices Syst., 2020

2019

Postbond Test of Through-Silicon Vias With Resistive Open Defects.

Rosa Rodríguez-Montañés, Daniel Arumí, Joan Figueras

IEEE Trans. Very Large Scale Integr. Syst., 2019

2017

Multi-Directional Space Tessellation to Improve the Decision Boundary in Indirect Mixed-Signal Testing.

Álvaro Gómez-Pau, Luz Balado, Joan Figueras

J. Electron. Test., 2017

Mitigating read & write errors in STT-MRAM memories under DVS.

Elena Ioana Vatajelu, Rosa Rodríguez-Montañés, Michel Renovell, Joan Figueras

Proceedings of the 22nd IEEE European Test Symposium, 2017

2016

Test Escapes of Stuck-Open Faults Caused by Parasitic Capacitances and Leakage Currents.

Daniel Arumí, Rosa Rodríguez-Montañés, Joan Figueras

IEEE Trans. Very Large Scale Integr. Syst., 2016

Prebond Testing of Weak Defects in TSVs.

Daniel Arumí, Rosa Rodríguez-Montañés, Joan Figueras

IEEE Trans. Very Large Scale Integr. Syst., 2016

Efficient Production Binning Using Octree Tessellation in the Alternate Measurements Space.

Álvaro Gómez-Pau, Luz Balado, Joan Figueras

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

Indirect test of M-S circuits using multiple specification band guarding.

Álvaro Gómez-Pau, Luz Balado, Joan Figueras

Integr., 2016

2015

Power-aware voltage tuning for STT-MRAM reliability.

Elena I. Vatajelu, Rosa Rodríguez-Montañés, Stefano Di Carlo, Marco Indaco, Michel Renovell, Paolo Prinetto, Joan Figueras

Proceedings of the 20th IEEE European Test Symposium, 2015

STT-MRAM cell reliability evaluation under process, voltage and temperature (PVT) variations.

Elena I. Vatajelu, Rosa Rodríguez-Montañés, Marco Indaco, Paolo Prinetto, Joan Figueras

Proceedings of the 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2015

Analog circuits testing using digitally coded indirect measurements.

Álvaro Gómez-Pau, Luz Balado, Joan Figueras

Proceedings of the 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2015

Read/write robustness estimation metrics for spin transfer torque (STT) MRAM cell.

Elena I. Vatajelu, Rosa Rodríguez-Montañés, Marco Indaco, Michel Renovell, Paolo Prinetto, Joan Figueras

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014

Sram cell stability metric under transient voltage noise.

Elena I. Vatajelu, Álvaro Gómez-Pau, Michel Renovell, Joan Figueras

Microelectron. J., 2014

Skew violation verification in digital interconnect signals based on signal addition.

Víctor H. Champac, Hector Villacorta, Nestor Hernandez, Joan Figueras

IEICE Electron. Express, 2014

Pre-bond testing of weak defects in TSVs.

Daniel Arumí, Rosa Rodríguez-Montañés, Joan Figueras

Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014

Post-bond test of Through-Silicon Vias with open defects.

Rosa Rodríguez-Montañés, Daniel Arumí, Joan Figueras

Proceedings of the 19th IEEE European Test Symposium, 2014

M-S specification binning based on digitally coded indirect measurements.

Álvaro Gómez-Pau, Luz Balado, Joan Figueras

Proceedings of the 19th IEEE European Test Symposium, 2014

Reliability estimation at block-level granularity of spin-transfer-torque MRAMs.

Stefano Di Carlo, Marco Indaco, Paolo Prinetto, Elena I. Vatajelu, Rosa Rodríguez-Montañés, Joan Figueras

Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014

2013

Diagnosis of Interconnect Full Open Defects in the Presence of Gate Leakage Currents.

Daniel Arumí, Rosa Rodríguez-Montañés, Joan Figueras, Stefan Eichenberger, Camelia Hora, Bram Kruseman

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

M-S test based on specification validation using octrees in the measure space.

Álvaro Gómez-Pau, Luz Balado, Joan Figueras

Proceedings of the 18th IEEE European Test Symposium, 2013

BIST architecture to detect defects in tsvs during pre-bond testing.

Daniel Arumí, Rosa Rodríguez-Montañés, Joan Figueras

Proceedings of the 18th IEEE European Test Symposium, 2013

2012

Efficiency evaluation of parametric failure mitigation techniques for reliable SRAM operation.

Elena I. Vatajelu, Joan Figueras

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2011

Gate Leakage Impact on Full Open Defects in Interconnect Lines.

Daniel Arumí, Rosa Rodríguez-Montañés, Joan Figueras, Stefan Eichenberger, Camelia Hora, Bram Kruseman

IEEE Trans. Very Large Scale Integr. Syst., 2011

Diagnosis of Interconnect Full Open Defects in the Presence of Fan-Out.

Daniel Arumí, Rosa Rodríguez-Montañés, Joan Figueras, Stefan Eichenberger, Camelia Hora, Bram Kruseman

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Unidirectional error detection, localization and correction for DRAMs: Application to on-line DRAM repair strategies.

Madalin Neagu, Liviu Miclea, Joan Figueras

Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011

New reliability mechanisms in memory design for sub-22nm technologies.

Nivard Aymerich, A. Asenov, Andrew R. Brown, Ramon Canal, Binjie Cheng, Joan Figueras, Antonio González, Enric Herrero, S. Markov, Miguel Miranda, Peyman Pouyan, Tanausú Ramírez, Antonio Rubio, Elena I. Vatajelu, Xavier Vera, Xingsheng Wang, Paul Zuber

Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011

Statistical analysis of 6T SRAM data retention voltage under process variation.

Elena Ioana Vatajelu, Joan Figueras

Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011

Robustness analysis of 6T SRAMs in memory retention mode under PVT variations.

Elena I. Vatajelu, Joan Figueras

Proceedings of the Design, Automation and Test in Europe, 2011

Transient Noise Failures in SRAM Cells: Dynamic Noise Margin Metric.

Elena I. Vatajelu, Álvaro Gómez-Pau, Michel Renovell, Joan Figueras

Proceedings of the 20th IEEE Asian Test Symposium, 2011

2010

Built-In Sensor for Signal Integrity Faults in Digital Interconnect Signals.

Víctor H. Champac, Victor Avendaño, Joan Figueras

IEEE Trans. Very Large Scale Integr. Syst., 2010

Parametric failure analysis of embedded SRAMs using fast & accurate dynamic analysis.

Elena I. Vatajelu, Georgios Panagopoulos, Kaushik Roy, Joan Figueras

Proceedings of the 15th European Test Symposium, 2010

Diagnosis of full open defects in interconnect lines with fan-out.

Rosa Rodríguez-Montañés, Daniel Arumí, Joan Figueras, Stefan Eichenberger, Camelia Hora, Bram Kruseman

Proceedings of the 15th European Test Symposium, 2010

Analog circuit test based on a digital signature.

Alvaro Gómez, Ricard Sanahuja, Luz Balado, Joan Figueras

Proceedings of the Design, Automation and Test in Europe, 2010

2009

Verifying Functional Specifications by Regression Techniques on Lissajous Test Signatures.

Luz Balado, Emili Lupon, Joan Figueras, Miquel Roca, Eugeni Isern, Rodrigo Picos

IEEE Trans. Circuits Syst. I Regul. Pap., 2009

Delay caused by resistive opens in interconnecting lines.

Daniel Arumí, Rosa Rodríguez-Montañés, Joan Figueras

Integr., 2009

2008

Experimental Characterization of CMOS Interconnect Open Defects.

Daniel Arumí, Rosa Rodríguez-Montañés, Joan Figueras

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Full Open Defects in Nanometric CMOS.

Daniel Arumí, Rosa Rodríguez-Montañés, Joan Figueras, Stefan Eichenberger, Camelia Hora, Bram Kruseman

Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008

Data Dependence of Delay Distribution for a Planar Bus.

Francesc Moll, Joan Figueras, Antonio Rubio

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2008

Time-dependent Behaviour of Full Open Defects in Interconnect Lines.

Rosa Rodríguez-Montañés, Daniel Arumí, Joan Figueras, Stefan Eichenberger, Camelia Hora, Bram Kruseman

Proceedings of the 2008 IEEE International Test Conference, 2008

2007

Minimizing Test Time in Arithmetic Test-Pattern Generators With Constrained Memory Resources.

Salvador Manich, Lucas Garcia-Deiros, Joan Figueras

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Diagnosis of Full Open Defects in Interconnecting Lines.

Rosa Rodríguez-Montañés, Daniel Arumí, Joan Figueras, Stefan Eichenberger, Camelia Hora, Bram Kruseman, Maurice Lousberg, Ananta K. Majhi

Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007

Diagnosis of Bridging Defects Based on Current Signatures at Low Power Supply Voltages.

Daniel Arumí, Rosa Rodríguez-Montañés, Joan Figueras, Stefan Eichenberger, Camelia Hora, Bram Kruseman, Maurice Lousberg, Ananta K. Majhi

Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007

2006

Lissajous Based Mixed-Signal Testing for N-Observable Signals.

Luz Balado, Emili Lupon, L. García, Rosa Rodríguez-Montañés, Joan Figueras

Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), 2006

2005

Testing Biquad Filters under Parametric Shifts Using X-Y Zoning.

R. Sanahuja, Victor Barcons, Luz Balado, Joan Figueras

J. Electron. Test., 2005

Defective behaviours of resistive opens in interconnect lines.

Daniel Arumí, Rosa Rodríguez-Montañés, Joan Figueras

Proceedings of the 10th European Test Symposium, 2005

2004

On High-Quality, Low Energy Built-In Self Test Preparation at RT-Level.

Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira, Salvador Manich, Luz Balado, Joan Figueras

J. Electron. Test., 2004

Analog Switches in Programmable Analog Devices: Quiescent Defective Behaviours.

Rosa Rodríguez-Montañés, D. Muñoz, Luz Balado, Joan Figueras

J. Electron. Test., 2004

BIST Technique by Equally Spaced Test Vector Sequences.

Salvador Manich, L. García, Luz Balado, Emili Lupon, Josep Rius, Rosa Rodríguez-Montañés, Joan Figueras

Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004

Signal integrity verification using high speed monitors.

Victor Avendaño, Víctor H. Champac, Joan Figueras

Proceedings of the 9th European Test Symposium, 2004

2003

Test Engineering Education in Europe: the EuNICE-Test Project.

Yves Bertrand, Marie-Lise Flottes, Luz Balado, Joan Figueras, Anton Biasizzo, Franc Novak, Stefano Di Carlo, Paolo Prinetto, Nicoleta Pricopi, Hans-Joachim Wunderlich, Jean-Pierre Van der Heyden

Proceedings of the 2003 International Conference on Microelectronics Systems Education, 2003

On the selection of efficient arithmetic additive test pattern generators [logic test].

Salvador Manich, L. García, Luz Balado, Emili Lupon, Josep Rius, Rosa Rodríguez-Montañés, Joan Figueras

Proceedings of the 8th European Test Workshop, 2003

Signal integrity loss in bus lines due to open shielding defects.

Victor Avendaño, Víctor H. Champac, Joan Figueras

Proceedings of the 8th European Test Workshop, 2003

2002

Leakage power bounds in CMOS digital technologies.

Antoni Ferré, Joan Figueras

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

On High-Quality, Low Energy BIST Preparation at RT-Level.

Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira, Salvador Manich, Luz Balado, Joan Figueras

Proceedings of the 3rd Latin American Test Workshop, 2002

RTL Level Preparation of High-Quality/Low-Energy/Low-Power BIST.

Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira, Salvador Manich, Rosa Rodríguez-Montañés, Joan Figueras

Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

2001

Detectability Conditions of Full Opens in the Interconnections.

Antonio Zenteno, Víctor H. Champac, Joan Figueras

J. Electron. Test., 2001

A Discussion on Test Pattern Generation for FPGA - Implemented Circuits.

Michel Renovell, Jean-Michel Portal, Penelope Faure, Joan Figueras, Yervant Zorian

J. Electron. Test., 2001

Guest Editorial.

Paolo Prinetto, Joan Figueras

J. Electron. Test., 2001

LEAP: An Accurate Defect-Free I_DDQ Estimator.

Antoni Ferré, Joan Figueras

J. Electron. Test., 2001

Digital Signature Proposal for Mixed-Signal Circuits.

Anna Maria Brosa, Joan Figueras

J. Electron. Test., 2001

Dynamic Signal X-Y Zoning and its Applicability to Detect Time Critical Defects in the Digital Domain.

Anotnio Zenteno, Víctor H. Champac, Joan Figueras

Proceedings of the 2nd Latin American Test Workshop, 2001

Test Challenges in a Nanometric World.

Joan Figueras

Proceedings of the 2nd Latin American Test Workshop, 2001

IS-FPGA : a new symmetric FPGA architecture with implicit scan.

Michel Renovell, Penelope Faure, Jean-Michel Portal, Joan Figueras, Yervant Zorian

Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

2000

Testing the Local Interconnect Resources of SRAM-Based FPGA's.

Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian

J. Electron. Test., 2000

An Approach to Minimize the Test Configuration for the Logic Cells of the Xilinx XC4000 FPGAs Family.

Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian

J. Electron. Test., 2000

Low Power BIST by Filtering Non-Detecting Vectors.

Salvador Manich, A. Gabarró, M. Lopez, Joan Figueras, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, João Paulo Teixeira, Marcelino B. Santos

J. Electron. Test., 2000

On Maximizing the Coverage of Catastrophic and Parametric Faults.

Anna Maria Brosa, Joan Figueras

J. Electron. Test., 2000

Some Experiments in Test Pattern Generation for FPGA-Implemented Combinational Circuits.

Michel Renovell, Jean-Michel Portal, Penelope Faure, Joan Figueras, Yervant Zorian

Proceedings of the 13th Annual Symposium on Integrated Circuits and Systems Design, 2000

Detectability Dependency on Test Generation Process for Interconnection Opens.

Antonio Zenteno, Víctor H. Champac, Joan Figueras

Proceedings of the 1st Latin American Test Workshop, 2000

Test Configuration Generation for FPGA Logic Cells.

Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian

Proceedings of the 1st Latin American Test Workshop, 2000

Analyzing the test generation problem for an application-oriented test of FPGAs.

Michel Renovell, Jean-Michel Portal, Penelope Faure, Joan Figueras, Yervant Zorian

Proceedings of the 5th European Test Workshop, 2000

TOF: a tool for test pattern generation optimization of an FPGA application oriented test.

Michel Renovell, Jean-Michel Portal, Penelope Faure, Joan Figueras, Yervant Zorian

Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

1999

SRAM-Based FPGAs: Testing the Embedded RAM Modules.

Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian

J. Electron. Test., 1999

IDDQ Testing of Opens in CMOS SRAMs.

Víctor H. Champac, José Castillejos, Joan Figueras

J. Electron. Test., 1999

Characterization of Floating Gate Defects in Analog Cells.

Anna Maria Brosa, Joan Figueras

J. Electron. Test., 1999

Low-energy BIST design: impact of the LFSR TPG parameters on the weighted switching activity.

Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Joan Figueras, Salvador Manich, João Paulo Teixeira, Marcelino B. Santos

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

On Optimizing Test Strategies for Analog Cells.

Anna Maria Brosa, Joan Figueras

Proceedings of the 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 1999

Test configuration minimization for the logic cells of SRAM-based FPGAs: a case study.

Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian

Proceedings of the 4th European Test Workshop, 1999

Exploring the Combination of IDDQ and iDDt Testing: Energy Testing.

Josep Rius, Joan Figueras

Proceedings of the 1999 Design, 1999

Testing the Configurable Interconnect/Logic Interface of SRAM-Based FPGA's.

Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian

Proceedings of the 1999 Design, 1999

Minimizing the Number of Test Configurations for Different FPGA Families.

Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian

Proceedings of the 8th Asian Test Symposium (ATS '99), 1999

1998

IDDQ testing: state of the art and future trends.

Antoni Ferré, Eugeni Isern, Josep Rius, Rosa Rodríguez-Montañés, Joan Figueras

Integr., 1998

Testing the Interconnect of RAM-Based FPGAs.

Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian

IEEE Des. Test Comput., 1998

SRAM-based FPGA's: testing the LUT/RAM modules.

Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian

Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

Characterization of leakage power in CMOS technologies.

Antoni Ferré, Joan Figueras

Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998

SRAM-Based FPGAs: A Fault Model for the Configurable Logig Modules.

Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian

Proceedings of the Field-Programmable Logic and Applications, 1998

Estimation of the Defective IDDQ Caused by Shorts in Deep-Submicron CMOS ICs.

Rosa Rodríguez-Montañés, Joan Figueras

Proceedings of the 1998 Design, 1998

RAM-Based FPGA's: A Test Approach for the Configurable Logic.

Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian

Proceedings of the 1998 Design, 1998

Novel Technique for Testing FPGAs.

Cecilia Metra, Michel Renovell, Giovanni A. Mojoli, Jean-Michel Portal, Sandro Pastore, Joan Figueras, Yervant Zorian, Davide Salvi, Giacomo R. Sechi

Proceedings of the 1998 Design, 1998

SRAM-Based FPGA's: Testing the Interconnect/Logic Interface.

Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian

Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998

1997

I_DDQ Detectable Bridges in Combinational CMOS Circuits.

Eugeni Isern, Joan Figueras

VLSI Design, 1997

Current Testing of CMOS Combinational Circuits with Single Floating Gate Defects.

Víctor H. Champac, Joan Figueras

VLSI Design, 1997

Fault-Secure Parity Prediction Arithmetic Operators.

Michael Nicolaidis, Ricardo de Oliveira Duarte, Salvador Manich, Joan Figueras

IEEE Des. Test Comput., 1997

Bridges in sequential CMOS circuits: current-voltage signatur.

Rosa Rodríguez-Montañés, Joan Figueras

Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997

Test of RAM-based FPGA: methodology and application to the interconnect.

Michel Renovell, Joan Figueras, Yervant Zorian

Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997

Power Dissipation During Testing: Should We Worry About it?

Vishwani D. Agrawal, Robert C. Aitken, J. Braden, Joan Figueras, S. Kumar, Hans-Joachim Wunderlich, Yervant Zorian

Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997

I_DDQ Characterization in Submicron CMOS.

Antoni Ferré, Joan Figueras

Proceedings of the Proceedings IEEE International Test Conference 1997, 1997

Maximizing the weighted switching activity in combinational CMOS circuits under the variable delay model.

Salvador Manich, Joan Figueras

Proceedings of the European Design and Test Conference, 1997

Test Pattern and Test Configuration Generation Methodology for the Logic of RAM-Based FPGA.

Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian

Proceedings of the 6th Asian Test Symposium (ATS '97), 17-18 November 1997, 1997

1996

Bridging defects resistance in the metal layer of a CMOS process.

Rosa Rodríguez-Montañés, E. M. J. G. Bruls, Joan Figueras

J. Electron. Test., 1996

Dynamic characterization of Built-In Current Sensors based on PN junctions: Analysis and experiments.

Josep Rius, Joan Figueras

J. Electron. Test., 1996

Enhancing realistic fault secureness in parity prediction array arithmetic operators by I_DDQ monitoring.

Salvador Manich, Michael Nicolaidis, Joan Figueras

Proceedings of the 14th IEEE VLSI Test Symposium (VTS'96), April 28, 1996

On estimating bounds of the quiescent current for I_DDQ testin.

Antoni Ferré, Joan Figueras

Proceedings of the 14th IEEE VLSI Test Symposium (VTS'96), April 28, 1996

Achieving Fault Secureness in Parity Prediction Arithmetic Operators: General Conditions and Implementations.

Michael Nicolaidis, Salvador Manich, Joan Figueras

Proceedings of the 1996 European Design and Test Conference, 1996

Power Optimization of Delay Constrained CMOS Bus Drivers.

S. Caufape, Joan Figueras

Proceedings of the 1996 European Design and Test Conference, 1996

1995

Current testing in dynamic CMOS circuits.

Joan Figueras, Michel Renovell

J. Electron. Test., 1995

IDDQ Test and Diagnosis of CMOS Circuits.

Eugeni Isern, Joan Figueras

IEEE Des. Test Comput., 1995

Detecting I_DDQ defective CMOS circuits by depowering.

Josep Rius, Joan Figueras

Proceedings of the 13th IEEE VLSI Test Symposium (VTS'95), April 30, 1995

Testability of floating gate defects in sequential circuits.

Víctor H. Champac, Joan Figueras

Proceedings of the 13th IEEE VLSI Test Symposium (VTS'95), April 30, 1995

Synthesis of I_DDQ-testable circuits: integrating built-in current sensors.

Hans-Joachim Wunderlich, M. Herzog, Joan Figueras, Juan A. Carrasco, Angel Calderón

Proceedings of the 1995 European Design and Test Conference, 1995

A built-in quiescent current monitor for CMOS VLSI circuits.

Antonio Rubio, Edmond Janssens, H. Casier, Joan Figueras, Diego Mateo, P. De Pauw, Jaume Segura

Proceedings of the 1995 European Design and Test Conference, 1995

1994

Electrical model of the floating gate defect in CMOS ICs: implications on I_DDQ testing.

Víctor H. Champac, Antonio Rubio, Joan Figueras

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994

Analysis of I_DDQ detectable bridges in combinational CMOS circuits.

Eugeni Isern, Joan Figueras

Proceedings of the 12th IEEE VLSI Test Symposium (VTS'94), 1994

Analysis of Bridging Defects in Sequential CMOS Circuits and their Current Testability.

Rosa Rodríguez-Montañés, Joan Figueras

Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

Test of Bridging Faults in Scan-based Sequential Circuits.

Eugeni Isern, Joan Figueras

Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

1993

Analysis of redundant structures in combinational circuits.

Eugeni Isern, Joan Figueras

Proceedings of the 11th IEEE VLSI Test Symposium (VTS'93), 1993

Test Generation with High Coverages for Quiescent Current Test of Bridging Faults in Combinational Circuits.

Eugeni Isern, Joan Figueras

Proceedings of the Proceedings IEEE International Test Conference 1993, Designing, Testing, and Diagnostics, 1993

Current Testing Viability in Dynamic CMOS Circuits.

Michel Renovell, Joan Figueras

Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1993

Analysis of the Floating Gate Defect in CMOS.

Víctor H. Champac, Antonio Rubio, Joan Figueras

Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1993

1992

Quiescent current analysis and experimentation of defective CMOS circuits.

Jaume A. Segura, Víctor H. Champac, Rosa Rodríguez-Montañés, Joan Figueras, J. A. Rubio

J. Electron. Test., 1992

Proportional BIC sensor for current testing.

Josep Rius, Joan Figueras

J. Electron. Test., 1992

Bridging Defects Resistance Measurements in a CMOS Process.

Rosa Rodríguez-Montañés, Joan Figueras, Eric Bruls

Proceedings of the Proceedings IEEE International Test Conference 1992, 1992

1991

Evaluation of safety-oriented two-version architectures.

Juan A. Carrasco, Joan Figueras, Annie Kuntzmann-Combelles

J. Syst. Softw., 1991

Current vs. Logic Testing of Gate Oxide Short, Floating Gate and Bridging Failures in CMOS.

Rosa Rodríguez-Montañés, Jaume A. Segura, Víctor H. Champac, Joan Figueras, J. A. Rubio

Proceedings of the Proceedings IEEE International Test Conference 1991, 1991