Vikram A. Saletore

Orcid: 0000-0001-8642-539X

According to our database1, Vikram A. Saletore authored at least 36 papers between 1989 and 2022.

Collaborative distances:

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2022
Reduced Precision Research of a GAN Image Generation Use-case.
Proceedings of the Pattern Recognition Applications and Methods, 2022

2021



Reduced Precision Strategies for Deep Learning: A High Energy Physics Generative Adversarial Network Use Case.
Proceedings of the 10th International Conference on Pattern Recognition Applications and Methods, 2021

2020




DeepGalaxy: Deducing the Properties of Galaxy Mergers from Images Using Deep Neural Networks.
Proceedings of the Fourth IEEE/ACM Workshop on Deep Learning on Supercomputers, 2020

2019



Efficient 8-Bit Quantization of Transformer Neural Machine Language Translation Model.
CoRR, 2019

Training Multiscale-CNN for Large Microscopy Image Classification in One Hour.
Proceedings of the High Performance Computing, 2019

Densifying Assumed-Sparse Tensors - Improving Memory Efficiency and MPI Collective Performance During Tensor Accumulation for Parallelized Training of Neural Machine Translation Models.
Proceedings of the High Performance Computing - 34th International Conference, 2019

2018
Distributed Training of Generative Adversarial Networks for Fast Detector Simulation.
Proceedings of the High Performance Computing, 2018

2017
Scale out for large minibatch SGD: Residual network training on ImageNet-1K with improved accuracy and reduced time to train.
CoRR, 2017

2013
HcBench: Methodology, Development, and Full-System Characterization of a Customer Usage Representative Big Data/Hadoop Benchmark.
Proceedings of the Advancing Big Data Benchmarks, 2013

HcBench: Methodology, development, and characterization of a customer usage representative big data/Hadoop benchmark.
Proceedings of the IEEE International Symposium on Workload Characterization, 2013

2006
Evaluating network processing efficiency with processor partitioning and asynchronous I/O.
Proceedings of the 2006 EuroSys Conference, Leuven, Belgium, April 18-21, 2006, 2006

2005
An Architecture for Software-Based iSCSI: Experiences and Analyses.
Proceedings of the NETWORKING 2005: Networking Technologies, 2005

Efficient Direct User Level Sockets for an Intel Xeon<sup>TM</sup> Processor Based TCP On-Load Engin.
Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005

An Architecture for Software-Based iSCSI on Multiprocessor Servers.
Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005

2004
ETA: Experience with an Intel Xeon Processor as a Packet Processing Engine.
IEEE Micro, 2004

2003
ETA: experience with an Intel® Xeon™ processor as a packet processing engine.
Proceedings of the 11th Annual IEEE Symposium on High Performance Interconnects, 2003

1996
Parallel Loop Scheduling With Data Prefetching On Distributed-Memory Machine.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 1996

1995
Message-driven parallel computations on the MEIKO CS-2 parallel supercomputer.
Proceedings of the High-Performance Computing and Networking, 1995

1994
Safe self-scheduling: A parallel loop scheduling scheme for shared-memory multiprocessors.
Int. J. Parallel Program., 1994

Parallel Computations on the CHARM Heterogeneous Workstation Cluster.
Proceedings of the Third International Symposium on High Performance Distributed Computing, 1994

1993
Self-scheduling on distributed-memory machines.
Proceedings of the Proceedings Supercomputing '93, 1993

1992
Prioritization in Parallel Symbolic Computing.
Proceedings of the Parallel Symbolic Computing: Languages, 1992

1991
Supporting Machine Independent Programming on Diverse Parallel Architectures.
Proceedings of the International Conference on Parallel Processing, 1991

1990
Parallel state-space search for a first solution with consistent linear speedups.
Int. J. Parallel Program., 1990

Consistent Linear Speedups to a First Solution in Parallel State-Space Search.
Proceedings of the 8th National Conference on Artificial Intelligence. Boston, Massachusetts, USA, July 29, 1990

1989
Obtaining First Solutions Faster in AND-OR Parallel Execution of Logic Programs.
Proceedings of the Logic Programming, 1989


  Loading...