Zehra Sura

According to our database1, Zehra Sura authored at least 38 papers between 2002 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2020
StackVault: Protection from Untrusted Functions.
Proceedings of the Second IEEE International Conference on Trust, 2020

2019
Data Transparency with Blockchain and AI Ethics.
ACM J. Data Inf. Qual., 2019

Using Structured Input and Modularity for Improved Learning.
CoRR, 2019

2018
An empirical study of the effect of source-level loop transformations on compiler stability.
Proc. ACM Program. Lang., 2018

NUMA-Aware Data-Transfer Measurements for Power/NVLink Multi-GPU Systems.
Proceedings of the High Performance Computing, 2018

Impact of System Resources on Performance of Deep Neural Network.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2018

Collaborative and Accountable Hardware Governance Using Blockchain.
Proceedings of the 4th IEEE International Conference on Collaboration and Internet Computing, 2018

2017
Leveraging OpenMP 4.5 Support in CLANG for Fortran.
Proceedings of the Scaling OpenMP for Exascale Performance and Portability, 2017

LORE: A loop repository for the evaluation of compilers.
Proceedings of the 2017 IEEE International Symposium on Workload Characterization, 2017

Rebooting the Data Access Hierarchy of Computing Systems.
Proceedings of the IEEE International Conference on Rebooting Computing, 2017

Efficient Fork-Join on GPUs Through Warp Specialization.
Proceedings of the 24th IEEE International Conference on High Performance Computing, 2017

2016
Performance Analysis and Optimization of Clang's OpenMP 4.5 GPU Support.
Proceedings of the 7th International Workshop on Performance Modeling, 2016

Offloading Support for OpenMP in Clang and LLVM.
Proceedings of the Third Workshop on the LLVM Compiler Infrastructure in HPC, 2016

Automatic Copying of Pointer-Based Data Structures.
Proceedings of the Languages and Compilers for Parallel Computing, 2016

Approximate computing: Challenges and opportunities.
Proceedings of the IEEE International Conference on Rebooting Computing, 2016

2015
Active Memory Cube: A processing-in-memory architecture for exascale systems.
IBM J. Res. Dev., 2015

Integrating GPU support for OpenMP offloading directives into Clang.
Proceedings of the Second Workshop on the LLVM Compiler Infrastructure in HPC, 2015

Performance analysis of OpenMP on a GPU using a CORAL proxy application.
Proceedings of the 6th International Workshop on Performance Modeling, 2015

Progressive Codesign of an Architecture and Compiler Using a Proxy Application.
Proceedings of the 27th International Symposium on Computer Architecture and High Performance Computing, 2015

Exploiting Fine- and Coarse-Grained Parallelism Using a Directive Based Approach.
Proceedings of the OpenMP: Heterogenous Execution and Data Movements, 2015

Data access optimization in a processing-in-memory system.
Proceedings of the 12th ACM International Conference on Computing Frontiers, 2015

2014
Coordinating GPU threads for OpenMP 4.0 in LLVM.
Proceedings of the 2014 LLVM Compiler Infrastructure in HPC, 2014

Using Multiple Threads to Accelerate Single Thread Performance.
Proceedings of the 2014 IEEE 28th International Parallel and Distributed Processing Symposium, 2014

2010
COMIC++: A software SVM system for heterogeneous multicore accelerator clusters.
Proceedings of the 16th International Conference on High-Performance Computer Architecture (HPCA-16 2010), 2010

2009
Design and implementation of software-managed caches for multicores with local memory.
Proceedings of the 15th International Conference on High-Performance Computer Architecture (HPCA-15 2009), 2009

2008
Supporting OpenMP on Cell.
Int. J. Parallel Program., 2008

Prefetching irregular references for software cache on cell.
Proceedings of the Sixth International Symposium on Code Generation and Optimization (CGO 2008), 2008

COMIC: a coherent shared memory interface for cell be.
Proceedings of the 17th International Conference on Parallel Architectures and Compilation Techniques, 2008

Hybrid access-specific software cache techniques for the cell BE architecture.
Proceedings of the 17th International Conference on Parallel Architectures and Compilation Techniques, 2008

2007
A Novel Asynchronous Software Cache Implementation for the Cell-BE Processor.
Proceedings of the Languages and Compilers for Parallel Computing, 2007

2006
Using advanced compiler technology to exploit the performance of the Cell Broadband Engine<sup>TM</sup> architecture.
IBM Syst. J., 2006

Optimizing the Use of Static Buffers for DMA on a CELL Chip.
Proceedings of the Languages and Compilers for Parallel Computing, 2006

2005
Compiler techniques for high performance sequentially consistent java programs.
Proceedings of the ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2005

Evaluating the Impact of Thread Escape Analysis on a Memory Consistency Model-Aware Compiler.
Proceedings of the Languages and Compilers for Parallel Computing, 2005

Optimizing Compiler for the CELL Processor.
Proceedings of the 14th International Conference on Parallel Architectures and Compilation Techniques (PACT 2005), 2005

2002
Automatic Implementation of Programming Language Consistency Models.
Proceedings of the Languages and Compilers for Parallel Computing, 15th Workshop, 2002

The Pensieve Project: A Compiler Infrastructure for Memory Models.
Proceedings of the International Symposium on Parallel Architectures, 2002

Instance-wise points-to analysis for loop-based dependence testing.
Proceedings of the 16th international conference on Supercomputing, 2002


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