Viktor Pus

According to our database, Viktor Pus authored at least 28 papers between 2009 and 2020.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2020

Multi Buses: Theory and Practical Considerations of Data Bus Width Scaling in FPGAs.

Lukás Kekely, Jakub Cabal, Viktor Pus, Jan Korenek

Proceedings of the 23rd Euromicro Conference on Digital System Design, 2020

2018

P4-To-VHDL: Automatic generation of high-speed input and output network blocks.

Pavel Benácek, Viktor Pus, Hana Kubátová, Tomás Cejka

Microprocess. Microsystems, 2018

Verification of Generated RTL from P4 Source Code.

Radek Isa, Pavel Benácek, Viktor Pus

Proceedings of the 2018 IEEE 26th International Conference on Network Protocols, 2018

Demonstration of Full-Duplex Packet Transfers Over PCI Express with Sustained 200 Gbps Throughput.

Lukás Kekely, Martin Spinler, Stepán Friedl, Jiri Sikora, Jan Korenek, Viktor Pus

Proceedings of the International Conference on Field-Programmable Technology, 2018

Configurable FPGA Packet Parser for Terabit Networks with Guaranteed Wire-Speed Throughput.

Jakub Cabal, Pavel Benácek, Lukas Kekely, Michal Kekely, Viktor Pus, Jan Korenek

Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2018

2017

Line rate programmable packet processing in 100Gb networks.

Pavel Benácek, Viktor Pus, Jan Korenek, Michal Kekely

Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

2016

Software Defined Monitoring of Application Protocols.

Lukas Kekely, Jan Kucera, Viktor Pus, Jan Korenek, Athanasios V. Vasilakos

IEEE Trans. Computers, 2016

High-speed regular expression matching with pipelined automata.

Denis Matousek, Jan Korenek, Viktor Pus

Proceedings of the 2016 International Conference on Field-Programmable Technology, 2016

P4-to-VHDL: Automatic Generation of 100 Gbps Packet Parsers.

Pavel Benácek, Viktor Pus, Hana Kubátová

Proceedings of the 24th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2016

Building a feedback loop to capture evidence of network incidents.

Zdenek Rosa, Tomás Cejka, Martin Zádník, Viktor Pus

Proceedings of the 12th International Conference on Network and Service Management, 2016

2015

High-density network flow monitoring.

Petr Velan, Viktor Pus

Proceedings of the IFIP/IEEE International Symposium on Integrated Network Management, 2015

Hardware accelerated flow measurement of 100 Gb ethernet.

Viktor Pus, Petr Velan, Lukas Kekely, Jan Korenek, Pavel Minarík

Proceedings of the IFIP/IEEE International Symposium on Integrated Network Management, 2015

2014

Software Defined Monitoring of application protocols.

Lukas Kekely, Viktor Pus, Jan Korenek

Proceedings of the 2014 IEEE Conference on Computer Communications, 2014

Trade-offs and progressive adoption of FPGA acceleration in network traffic monitoring.

Lukas Kekely, Viktor Pus, Pavel Benácek, Jan Korenek

Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

Using DSP blocks to compute CRC hash in FPGA (abstract only).

Viktor Pus, Lukas Kekely, Tomás Závodník

Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2014

Application specific processor with high level synthesized instructions (abstract only).

Viktor Pus, Pavel Benácek

Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2014

Architecture of Effective High-Speed Network Stream Merger.

Pavel Benácek, Hana Kubátová, Viktor Pus

Proceedings of the 17th Euromicro Conference on Digital System Design, 2014

CRC based hashing in FPGA using DSP blocks.

Tomás Závodník, Lukas Kekely, Viktor Pus

Proceedings of the 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2014

Design methodology of configurable high performance packet parser for FPGA.

Viktor Pus, Lukas Kekely, Jan Korenek

Proceedings of the 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2014

2012

Algoritmy klasifikace paketů ; Packet Classification Algorithms.

Viktor Pus

PhD thesis, 2012

Reducing memory in high-speed packet classification.

Viktor Pus, Jan Korenek

Proceedings of the 8th International Wireless Communications and Mobile Computing Conference, 2012

Low-latency modular packet header parser for FPGA.

Viktor Pus, Lukas Kekely, Jan Korenek

Proceedings of the Symposium on Architecture for Networking and Communications Systems, 2012

Hardware Acceleration for Measurements in 100 Gb/s Networks.

Viktor Pus

Proceedings of the Dependable Networks and Services, 2012

2011

Hardware architecture for packet classification with prefix coloring.

Viktor Pus, Michal Kajan, Jan Korenek

Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011

Netbench: Framework for Evaluation of Packet Processing Algorithms.

Viktor Pus, Jiri Tobola, Vlastimil Kosar, Jan Kastil, Jan Korenek

Proceedings of the 2011 ACM/IEEE Symposium on Architectures for Networking and Communications Systems (ANCS), 2011

2010

Memory optimizations for packet classification algorithms in FPGA.

Viktor Pus, Juraj Blaho, Jan Korenek

Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010

2009

Fast and scalable packet classification using perfect hash functions.

Viktor Pus, Jan Korenek

Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, 2009

Memory optimization for packet classification algorithms.

Juraj Blaho, Jan Korenek, Viktor Pus

Proceedings of the 2009 ACM/IEEE Symposium on Architecture for Networking and Communications Systems, 2009