Michal Kekely

According to our database, Michal Kekely authored at least 9 papers between 2017 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2023

Optimizing Packet Classification on FPGA.

Michal Kekely, Jan Korenek

Proceedings of the 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2023

2020

General memory efficient packet matching FPGA architecture for future high-speed networks.

Michal Kekely, Lukás Kekely, Jan Korenek

Microprocess. Microsystems, 2020

Pipelined ALU for effective external memory access in FPGA.

Tomás Benes, Michal Kekely, Karel Hynek, Tomás Cejka

Proceedings of the 23rd Euromicro Conference on Digital System Design, 2020

2018

Configurable FPGA Packet Parser for Terabit Networks with Guaranteed Wire-Speed Throughput.

Jakub Cabal, Pavel Benácek, Lukas Kekely, Michal Kekely, Viktor Pus, Jan Korenek

Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2018

Memory Aware Packet Matching Architecture for High-Speed Networks.

Michal Kekely, Lukas Kekely, Jan Korenek

Proceedings of the 21st Euromicro Conference on Digital System Design, 2018

200 Gbps Hardware Accelerated Encryption System for FPGA Network Cards.

Zdenek Martinasek, Jan Hajny, David Smekal, Lukas Malina, Denis Matousek, Michal Kekely, Nele Mentens

Proceedings of the 2018 Workshop on Attacks and Solutions in Hardware Security, 2018

2017

Mapping of P4 match action tables to FPGA.

Michal Kekely, Jan Korenek

Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

Line rate programmable packet processing in 100Gb networks.

Pavel Benácek, Viktor Pus, Jan Korenek, Michal Kekely

Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

Packet Classification with Limited Memory Resources.

Michal Kekely, Jan Korenek

Proceedings of the Euromicro Conference on Digital System Design, 2017