Jan Korenek

Orcid: 0000-0002-4662-7349

According to our database1, Jan Korenek authored at least 82 papers between 2005 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
Analysis of TLS Prefiltering for IDS Acceleration.
Proceedings of the Passive and Active Measurement - 24th International Conference, 2023

Accelerating IDS Using TLS Pre-Filter in FPGA.
Proceedings of the IEEE Symposium on Computers and Communications, 2023

400G Ethernet Packet Capture Demo Based on Network Development Kit for FPGAs.
Proceedings of the IEEE INFOCOM 2023, 2023

Optimizing Packet Classification on FPGA.
Proceedings of the 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2023

2022
ClassBench-ng: Benchmarking Packet Classification Algorithms in the OpenFlow Era.
IEEE/ACM Trans. Netw., 2022

FPL Demo: 400G FPGA Packet Capture Based on Network Development Kit.
Proceedings of the 32nd International Conference on Field-Programmable Logic and Applications, 2022

2021
Scalability of Hash-Based Pattern Matching for High-Speed Network Security and Monitoring.
Proceedings of the IEEE Symposium on Computers and Communications, 2021

Increasing Memory Efficiency of Hash-Based Pattern Matching for High-Speed Networks.
Proceedings of the International Conference on Field-Programmable Technology, 2021

Efficient Acceleration of Decision Tree Algorithms for Encrypted Network Traffic Analysis.
Proceedings of the 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2021

2020
General memory efficient packet matching FPGA architecture for future high-speed networks.
Microprocess. Microsystems, 2020

Enabling Event-Triggered Data Plane Monitoring.
Proceedings of the SOSR '20: Symposium on SDN Research, San Jose, CA, USA, March 3, 2020, 2020

Increasing Throughput of Intrusion Detection Systems by Hash-Based Short String Pre-filter.
Proceedings of the 45th IEEE Conference on Local Computer Networks, 2020

Multi Buses: Theory and Practical Considerations of Data Bus Width Scaling in FPGAs.
Proceedings of the 23rd Euromicro Conference on Digital System Design, 2020

2019
Deep Packet Inspection in FPGAs via Approximate Nondeterministic Automata.
CoRR, 2019

Deep Packet Inspection in FPGAs via Approximate Nondeterministic Automata.
Proceedings of the 27th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2019

Acceleration of Feature Extraction for Real-Time Analysis of Encrypted Network Traffic.
Proceedings of the 22nd IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2019

Hash-based Pattern Matching for High Speed Networks.
Proceedings of the 22nd IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2019

Effective FPGA Architecture for General CRC.
Proceedings of the Architecture of Computing Systems - ARCS 2019, 2019

2018
Seek and Push: Detecting Large Traffic Aggregates in the Dataplane.
CoRR, 2018

Live demonstration of FPGA based networking accelerator for 200 Gbps data transfers.
Proceedings of the 2018 IEEE/IFIP Network Operations and Management Symposium, 2018

General IDS Acceleration for High-Speed Networks.
Proceedings of the 36th IEEE International Conference on Computer Design, 2018

Demonstration of Full-Duplex Packet Transfers Over PCI Express with Sustained 200 Gbps Throughput.
Proceedings of the International Conference on Field-Programmable Technology, 2018

High-Speed Computation of CRC Codes for FPGAs.
Proceedings of the International Conference on Field-Programmable Technology, 2018

Accelerated Wire-Speed Packet Capture at 200 Gbps.
Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018

Configurable FPGA Packet Parser for Terabit Networks with Guaranteed Wire-Speed Throughput.
Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2018

High-Speed Regular Expression Matching with Pipelined Memory-Based Automata.
Proceedings of the 26th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2018

Memory Aware Packet Matching Architecture for High-Speed Networks.
Proceedings of the 21st Euromicro Conference on Digital System Design, 2018

Regular expression matching with pipelined delayed input DFAs for high-speed networks.
Proceedings of the 2018 Symposium on Architectures for Networking and Communications Systems, 2018

2017
Evolutionary design of hash function pairs for network filters.
Appl. Soft Comput., 2017

Mapping of P4 match action tables to FPGA.
Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

Line rate programmable packet processing in 100Gb networks.
Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

Packet Classification with Limited Memory Resources.
Proceedings of the Euromicro Conference on Digital System Design, 2017

ClassBench-ng: Recasting ClassBench after a Decade of Network Evolution.
Proceedings of the ACM/IEEE Symposium on Architectures for Networking and Communications Systems, 2017

2016
Software Defined Monitoring of Application Protocols.
IEEE Trans. Computers, 2016

Evolutionary circuit design for fast FPGA-based classification of network application protocols.
Appl. Soft Comput., 2016

Adaptive development of hash functions in FPGA-based network routers.
Proceedings of the 2016 IEEE Symposium Series on Computational Intelligence, 2016

High-speed regular expression matching with pipelined automata.
Proceedings of the 2016 International Conference on Field-Programmable Technology, 2016

Packet processing on FPGA SoC with DPDK.
Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

Dynamically Reconfigurable Architecture with Atomic Configuration Updates for Flexible Regular Expressions Matching in FPGA.
Proceedings of the 2016 Euromicro Conference on Digital System Design, 2016

Evaluating Reputation of Internet Entities.
Proceedings of the Management and Security in the Age of Hyperconnectivity, 2016

2015
Evolution of Non-Cryptographic Hash Function Pairs for FPGA-Based Network Applications.
Proceedings of the IEEE Symposium Series on Computational Intelligence, 2015

Hardware accelerated flow measurement of 100 Gb ethernet.
Proceedings of the IFIP/IEEE International Symposium on Integrated Network Management, 2015

A Fast FPGA-Based Classification of Application Protocols Optimized Using Cartesian GP.
Proceedings of the Applications of Evolutionary Computation - 18th European Conference, 2015

Towards Efficient Field Programmable Pattern Matching Array.
Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015

2014
Software Defined Monitoring of application protocols.
Proceedings of the 2014 IEEE Conference on Computer Communications, 2014

Trade-offs and progressive adoption of FPGA acceleration in network traffic monitoring.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

Design methodology of configurable high performance packet parser for FPGA.
Proceedings of the 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2014

On NFA-split architecture optimizations.
Proceedings of the 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2014

Fast lookup for dynamic packet filtering in FPGA.
Proceedings of the 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2014

Low latency book handling in FPGA for high frequency trading.
Proceedings of the 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2014

Network monitoring probe based on Xilinx Zynq.
Proceedings of the tenth ACM/IEEE symposium on Architectures for networking and communications systems, 2014

2013
NFA reduction for regular expressions matching using FPGA.
Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013

Memory efficient IP lookup in 100 GBPS networks.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

Towards hardware architecture for memory efficient IPv4/IPv6 Lookup in 100 Gbps networks.
Proceedings of the 16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2013

Hardware acceleration in computer networks.
Proceedings of the 16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2013

Hardware architecture for the fast pattern matching.
Proceedings of the 16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2013

Framework for fast prototyping of applications running on reconfigurable system on chip.
Proceedings of the 2013 Conference on Design and Architectures for Signal and Image Processing, 2013

2012
Reducing memory in high-speed packet classification.
Proceedings of the 8th International Wireless Communications and Mobile Computing Conference, 2012

Low-latency modular packet header parser for FPGA.
Proceedings of the Symposium on Architecture for Networking and Communications Systems, 2012

A new embedded platform for rapid development of network applications.
Proceedings of the Symposium on Architecture for Networking and Communications Systems, 2012

2011
Effective hash-based IPv6 longest prefix match.
Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011

Hardware architecture for packet classification with prefix coloring.
Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011

Reduction of FPGA resources for regular expression matching by relation similarity.
Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011

Netbench: Framework for Evaluation of Packet Processing Algorithms.
Proceedings of the 2011 ACM/IEEE Symposium on Architectures for Networking and Communications Systems (ANCS), 2011

2010
Memory optimizations for packet classification algorithms in FPGA.
Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010

Efficient mapping of nondeterministic automata to FPGA for fast regular expression matching.
Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010

Hardware accelerated pattern matching based on Deterministic Finite Automata with perfect hashing.
Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010

NFA split architecture for fast regular expression matching.
Proceedings of the 2010 ACM/IEEE Symposium on Architecture for Networking and Communications Systems, 2010

High speed pattern matching algorithm based on deterministic finite automata with faulty transition table.
Proceedings of the 2010 ACM/IEEE Symposium on Architecture for Networking and Communications Systems, 2010

Efficient packet classification algorithm based on entropy.
Proceedings of the 2010 ACM/IEEE Symposium on Architecture for Networking and Communications Systems, 2010

2009
Fast and scalable packet classification using perfect hash functions.
Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, 2009

Methodology for Fast Pattern Matching by Deterministic Finite Automaton with Perfect Hashing.
Proceedings of the 12th Euromicro Conference on Digital System Design, 2009

Packet header analysis and field extraction for multigigabit networks.
Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2009

Memory optimization for packet classification algorithms.
Proceedings of the 2009 ACM/IEEE Symposium on Architecture for Networking and Communications Systems, 2009

2008
GICS: Generic interconnection system.
Proceedings of the FPL 2008, 2008

Network Probe for Flexible Flow Monitoring.
Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), 2008

2007
FlowContext: Flexible Platform for Multigigabit Stateful Packet Processing.
Proceedings of the FPL 2007, 2007

Online Protocol Testing for FPGA Based Fault Tolerant Systems.
Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007

Intrusion Detection System Intended for Multigigabit Networks.
Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), 2007

2006
A Flexible Technique for the Automatic Design of Approximate String Matching Architectures.
Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), 2006

2005
Intrinsic Evolution of Sorting Networks: A Novel Complete Hardware Implementation for FPGAs.
Proceedings of the Evolvable Systems: From Biology to Hardware, 2005

NetFlow Probe Intended for High-Speed Networks.
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005


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