Viktor Schuppan

Orcid: 0000-0001-5638-3678

Affiliations:
  • ETH Zurich, Switzerland


According to our database1, Viktor Schuppan authored at least 21 papers between 2000 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

Online presence:

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Bibliography

2020
Enhanced Unsatisfiable Cores for QBF: Weakening Universal to Existential Quantifiers.
Int. J. Artif. Intell. Tools, 2020

2016
Enhancing unsatisfiable cores for LTL with information on temporal relevance.
Theor. Comput. Sci., 2016

Extracting unsatisfiable cores for LTL via temporal resolution.
Acta Informatica, 2016

2012
Towards a notion of unsatisfiable and unrealizable cores for LTL.
Sci. Comput. Program., 2012

2011
Evaluating LTL Satisfiability Solvers.
Proceedings of the Automated Technology for Verification and Analysis, 2011

2010
RATSY - A New Requirements Analysis Tool with Synthesis.
Proceedings of the Computer Aided Verification, 22nd International Conference, 2010

2009
Towards a Notion of Unsatisfiable Cores for LTL.
Proceedings of the Fundamentals of Software Engineering, 2009

2008
Diagnostic Information for Realizability.
Proceedings of the Verification, 2008

Survey on Directed Model Checking.
Proceedings of the Model Checking and Artificial Intelligence, 5th International Workshop, 2008

2007
Boolean Abstraction for Temporal Logic Satisfiability.
Proceedings of the Computer Aided Verification, 19th International Conference, 2007

2006
Liveness checking as safety checking to find shortest counterexamples to linear time properties.
PhD thesis, 2006

Linear Encodings of Bounded LTL Model Checking.
Log. Methods Comput. Sci., 2006

2005
Liveness Checking as Safety Checking for Infinite State Spaces.
Proceedings of the 7th International Workshop on Verification of Infinite-State Systems, 2005

Shortest Counterexamples for Symbolic Model Checking of LTL with Past.
Proceedings of the Tools and Algorithms for the Construction and Analysis of Systems, 2005

2004
Efficient reduction of finite state model checking to reachability analysis.
Int. J. Softw. Tools Technol. Transf., 2004

JVM Independent Replay in Java.
Proceedings of the Fourth Workshop on Runtime Verification, 2004

JNuke: Efficient Dynamic Analysis for Java.
Proceedings of the Computer Aided Verification, 16th International Conference, 2004

2003
Verifying the IEEE 1394 FireWire Tree Identify Protocol with SMV.
Formal Aspects Comput., 2003

Formal Methods Group ETH Zürich.
Proceedings of the Eighth International Workshop on Formal Methods for Industrial Critical Systems, 2003

2002
Liveness Checking as Safety Checking.
Proceedings of the 7th International ERCIM Workshop in Formal Methods for Industrial Critical Systems, 2002

2000
A CMM-Based Evaluation of the V-Model 97.
Proceedings of the Software Process Technology, 7th European Workshop, 2000


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