Robert Könighofer

According to our database1, Robert Könighofer
  • authored at least 37 papers between 2008 and 2017.
  • has a "Dijkstra number"2 of four.

Timeline

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Bibliography

2017
The first reactive synthesis competition (SYNTCOMP 2014).
STTT, 2017

2016
The 3rd Reactive Synthesis Competition (SYNTCOMP 2016): Benchmarks, Participants & Results.
Proceedings of the Proceedings Fifth Workshop on Synthesis, 2016

Satisfiability-Based Methods for Reactive Synthesis from Safety Specifications.
CoRR, 2016

Synthesis of Admissible Shields.
Proceedings of the Hardware and Software: Verification and Testing, 2016

Synthesizing adaptive test strategies from temporal logic specifications.
Proceedings of the 2016 Formal Methods in Computer-Aided Design, 2016

Designing reliable cyber-physical systems overview associated to the special session at FDL'16.
Proceedings of the 2016 Forum on Specification and Design Languages, 2016

SMT-Based CPS Parameter Synthesis.
Proceedings of the ARCH@CPSWeek 2016, 2016

2015
The Second Reactive Synthesis Competition (SYNTCOMP 2015).
Proceedings of the Proceedings Fourth Workshop on Synthesis, 2015

The First Reactive Synthesis Competition (SYNTCOMP 2014).
CoRR, 2015

Shield Synthesis: Runtime Enforcement for Reactive Systems.
CoRR, 2015

Cooperative Reactive Synthesis.
CoRR, 2015

Shield Synthesis: - Runtime Enforcement for Reactive Systems.
Proceedings of the Tools and Algorithms for the Construction and Analysis of Systems, 2015

Assume-Guarantee Synthesis for Concurrent Reactive Programs with Partial Information.
Proceedings of the Tools and Algorithms for the Construction and Analysis of Systems, 2015

Synthesizing cooperative reactive mission plans.
Proceedings of the 2015 IEEE/RSJ International Conference on Intelligent Robots and Systems, 2015

Cooperative Reactive Synthesis.
Proceedings of the Automated Technology for Verification and Analysis, 2015

2014
Automatic Error Localization for Software using Deductive Verification.
CoRR, 2014

SAT-Based Methods for Circuit Synthesis.
CoRR, 2014

How to Handle Assumptions in Synthesis.
Proceedings of the Proceedings 3rd Workshop on Synthesis, 2014

Assume-Guarantee Synthesis for Concurrent Reactive Programs with Partial Information.
CoRR, 2014

Synthesizing robust systems.
Acta Inf., 2014

SAT-Based Synthesis Methods for Safety Specs.
Proceedings of the Verification, Model Checking, and Abstract Interpretation, 2014

Automating Test-Suite Augmentation.
Proceedings of the 2014 14th International Conference on Quality Software, 2014

Automatic Error Localization for Software Using Deductive Verification.
Proceedings of the Hardware and Software: Verification and Testing, 2014

Synthesis of synchronization using uninterpreted functions.
Proceedings of the Formal Methods in Computer-Aided Design, 2014

SAT-based methods for circuit synthesis.
Proceedings of the Formal Methods in Computer-Aided Design, 2014

Partial witnesses from preprocessed quantified Boolean formulas.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013
Debugging formal specifications: a practical approach using model-based diagnosis and counterstrategies.
STTT, 2013

SAT-Based Synthesis Methods for Safety Specs.
CoRR, 2013

2012
Synthesizing Robust Systems with RATSY
Proceedings of the Proceedings First Workshop on Synthesis, 2012

Repair with On-The-Fly Program Analysis.
Proceedings of the Hardware and Software: Verification and Testing, 2012

FoREnSiC- An Automatic Debugging Environment for C Programs.
Proceedings of the Hardware and Software: Verification and Testing, 2012

Symbolically synthesizing small circuits.
Proceedings of the Formal Methods in Computer-Aided Design, 2012

2011
Automated error localization and correction for imperative programs.
Proceedings of the International Conference on Formal Methods in Computer-Aided Design, 2011

2010
Debugging Unrealizable Specifications with Model-Based Diagnosis.
Proceedings of the Hardware and Software: Verification and Testing, 2010

RATSY - A New Requirements Analysis Tool with Synthesis.
Proceedings of the Computer Aided Verification, 22nd International Conference, 2010

2009
Debugging formal specifications using simple counterstrategies.
Proceedings of 9th International Conference on Formal Methods in Computer-Aided Design, 2009

2008
A Fast and Cache-Timing Resistant Implementation of the AES.
Proceedings of the Topics in Cryptology, 2008


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