Vineesh V. S.

Orcid: 0000-0001-9960-0601

According to our database1, Vineesh V. S. authored at least 8 papers between 2017 and 2022.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

2022
Aries: A Semiformal Technique for Fine-Grained Bug Localization in Hardware Designs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

2021
Enhanced Design Debugging With Assistance From Guidance-Based Model Checking.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

Enhancing Testbench Quality via Genetic Algorithm.
Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021

2020
Analyzing Hardware Security Properties of Processors through Model Checking.
Proceedings of the 33rd International Conference on VLSI Design and 19th International Conference on Embedded Systems, 2020

LUT-based Circuit Approximation with Targeted Error Guarantees.
Proceedings of the 29th IEEE Asian Test Symposium, 2020

2019
Identification of Effective Guidance Hints for Better Design Debugging by Formal Methods.
Proceedings of the VLSI Design and Test - 23rd International Symposium, 2019

Orion: A Technique to Prune State Space Search Directions for Guidance-Based Formal Verification.
Proceedings of the 28th IEEE Asian Test Symposium, 2019

2017
Achieving full functional coverage for the forwarding unit of pipelined processors.
Proceedings of the 2017 IEEE East-West Design & Test Symposium, 2017


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