Vishnu C. Vimjam

According to our database1, Vishnu C. Vimjam authored at least 8 papers between 2005 and 2007.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

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Bibliography

2007
Strategies for SAT-Based Formal Verification.
PhD thesis, 2007

Using Scan-Dump Values to Improve Functional-Diagnosis Methodology.
Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007

Explicit Safety Property Strengthening in SAT-based Induction.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

2006
Efficient Fault Collapsing via Generalized Dominance Relations.
Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

A Study of Implication Based Pseudo Functional Testing.
Proceedings of the 2006 IEEE International Test Conference, 2006

Fast illegal state identification for improving SAT-based induction.
Proceedings of the 43rd Design Automation Conference, 2006

2005
Increasing the deducibility in CNF instances for efficient SAT-based bounded model checking.
Proceedings of the Tenth IEEE International High-Level Design Validation and Test Workshop 2005, Napa Valley, CA, USA, November 30, 2005

Untestable fault identification through enhanced necessary value assignments.
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005


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