Sreejit Chakravarty

According to our database, Sreejit Chakravarty authored at least 125 papers between 1986 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2023

IP Session on Chiplet: Design, Assembly, and Test.

Bapi Vinnakota, Jaber Derakhshandeh, Eric Beyne, Erik Jan Marinissen, Sreejit Chakravarty

Proceedings of the 41st IEEE VLSI Test Symposium, 2023

Silent Data Errors: Sources, Detection, and Modeling.

Adit D. Singh, Sreejit Chakravarty, George Papadimitriou, Dimitris Gizopoulos

Proceedings of the 41st IEEE VLSI Test Symposium, 2023

Effective and Efficient Testing of Large Numbers of Inter-Die Interconnects in Chiplet-Based Multi-Die Packages.

Po-Yao Chuang, Francesco Lorenzelli, Sreejit Chakravarty, Cheng-Wen Wu, Georges G. E. Gielen, Erik Jan Marinissen

Proceedings of the 41st IEEE VLSI Test Symposium, 2023

Effective and Efficient Test and Diagnosis Pattern Generation for Many Inter-Die Interconnects in Chiplet-Based Packages.

Po-Yao Chuang, Francesco Lorenzelli, Sreejit Chakravarty, Slimane Boutobza, Cheng-Wen Wu, Georges G. E. Gielen, Erik Jan Marinissen

Proceedings of the IEEE International 3D Systems Integration Conference, 2023

2022

Special Session: A Call to Standardize Chip-let Interconnect Testing.

Sreejit Chakravarty

Proceedings of the 40th IEEE VLSI Test Symposium, 2022

2020

Testing of Prebond Through Silicon Vias.

Sourav Das, Fei Su, Sreejit Chakravarty

IEEE Des. Test, 2020

Internal I/O Testing: Definition and a Solution.

Sreejit Chakravarty, Fei Su, Indira A. Gohad, Sudheer V. Bandana, B. S. Adithya, Wei Ming Lim

Proceedings of the 38th IEEE VLSI Test Symposium, 2020

2019

A Comparative Study of Pre-bond TSV Test Methodologies.

Sourav Das, Fei Su, Sreejit Chakravarty

Proceedings of the 37th IEEE VLSI Test Symposium, 2019

2018

Innovative practices on functional testing and fault simulation for FuSa.

Anandh Krishnan, John van Gelder, Mayukh Bhattacharya, Sreejit Chakravarty, Prashant Goteti

Proceedings of the 36th IEEE VLSI Test Symposium, 2018

Innovative practices on memory test practice.

M. Casarsa, Gurgen Harutyunyan, Kaitlyn Chen, Ramesh Sharma, Giri Podichetty, Martin Keim, Sreejit Chakravarty, Ramesh C. Tekumalla

Proceedings of the 36th IEEE VLSI Test Symposium, 2018

A PVT-Resilient No-Touch DFT Methodology for Prebond TSV Testing.

Sourav Das, Fei Su, Sreejit Chakravarty

Proceedings of the IEEE International Test Conference, 2018

2017

Innovative practices session 6C DFT for functional safety.

Prashant Goteti, Sreejit Chakravarty

Proceedings of the 35th IEEE VLSI Test Symposium, 2017

2016

Microarray medical data classification using kernel ridge regression and modified cat swarm optimization based gene selection system.

P. Mohapatra, Sreejit Chakravarty, P. K. Dash

Swarm Evol. Comput., 2016

Evolutionary extreme learning machine for energy price forecasting.

Sreejit Chakravarty, P. Mohapatra, Pradipta Kishore Dash

Int. J. Knowl. Based Intell. Eng. Syst., 2016

A Hybrid Kernel Extreme Learning Machine and Improved Cat Swarm Optimization for Microarray Medical Data Classification.

Sreejit Chakravarty, Ranjeeta Bisoi, P. K. Dash

Int. J. Appl. Evol. Comput., 2016

2015

An improved cuckoo search based extreme learning machine for medical data classification.

P. Mohapatra, Sreejit Chakravarty, Pradipta K. Dash

Swarm Evol. Comput., 2015

2014

Silicon Evaluation of Cell-Aware ATPG Tests and Small Delay Tests.

Fan Yang, Sreejit Chakravarty, Arun Gunda, Nicole Wu, Jianyu Ning

Proceedings of the 23rd IEEE Asian Test Symposium, 2014

2013

Power-safe application of tdf patterns to flip-chip designs during wafer test.

Wei Zhao, Junxia Ma, Mohammad Tehranipoor, Sreejit Chakravarty

ACM Trans. Design Autom. Electr. Syst., 2013

Innovative practices session 2C: Memory test.

Charutosh Dixit, Ramesh C. Tekumalla, Sreejit Chakravarty, Manuel d'Abreu, Zhuoyu Bao, Concetta Riccobene

Proceedings of the 31st IEEE VLSI Test Symposium, 2013

2012

Ensuring Power-Safe Application of Test Patterns Using an Effective Gating Approach Considering Current Limits.

Wei Zhao, Mohammad Tehranipoor, Sreejit Chakravarty

J. Low Power Electron., 2012

Layout-Aware Pattern Evaluation and Analysis for Power-Safe Application of Transition Delay Fault Patterns.

Hassan Salmani, Wei Zhao, Mohammad Tehranipoor, Sreejit Chakravarty, Patrick Girard, Xiaoqing Wen

J. Low Power Electron., 2012

Evolutionary functional link interval type-2 fuzzy neural system for exchange rate prediction.

Sreejit Chakravarty, Pradipta K. Dash

Int. J. Data Min. Model. Manag., 2012

A PSO based integrated functional link net and interval type-2 fuzzy logic system for predicting stock market indices.

Sreejit Chakravarty, Pradipta K. Dash

Appl. Soft Comput., 2012

A novel method for fast identification of peak current during test.

Wei Zhao, Sreejit Chakravarty, Junxia Ma, Narendra Devta-Prasanna, Fan Yang, Mohammad Tehranipoor

Proceedings of the 30th IEEE VLSI Test Symposium, 2012

Silicon evaluation of faster than at-speed transition delay tests.

Sreejit Chakravarty, Narendra Devta-Prasanna, Arun Gunda, Junxia Ma, Fan Yang, H. Guo, R. Lai, D. Li

Proceedings of the 30th IEEE VLSI Test Symposium, 2012

2011

An Evolutionary Functional Link Neural Fuzzy Model for Financial Time Series Forecasting.

Sreejit Chakravarty, Pradipta K. Dash, V. Ravikumar Pandi, Bijaya K. Panigrahi

Int. J. Appl. Evol. Comput., 2011

Dynamic filter weights neural network model integrated with differential evolution for day-ahead price forecasting in energy market.

Sreejit Chakravarty, Pradipta K. Dash

Expert Syst. Appl., 2011

Power-safe test application using an effective gating approach considering current limits.

Wei Zhao, Mohammad Tehranipoor, Sreejit Chakravarty

Proceedings of the 29th IEEE VLSI Test Symposium, 2011

Optimal manufacturing flow to determine minumum operating voltage.

Sreejit Chakravarty, Binh Dang, Darcy Escovedo, A. J. Haas

Proceedings of the 2011 IEEE International Test Conference, 2011

A Process Monitor Based Speed Binning and Die Matching Algorithm.

Sreejit Chakravarty

Proceedings of the 20th IEEE Asian Test Symposium, 2011

2010

Impact of multiple input switching on delay test under process variation.

Sean H. Wu, Sreejit Chakravarty, Li-C. Wang

Proceedings of the 28th IEEE VLSI Test Symposium, 2010

Special session 11C: Hot topic design consideration and silicon evaluation of on-chip monitors.

Sreejit Chakravarty

Proceedings of the 28th IEEE VLSI Test Symposium, 2010

Testing of latch based embedded arrays using scan tests.

Fan Yang, Sreejit Chakravarty

Proceedings of the 2011 IEEE International Test Conference, 2010

Power-Safe Application of Transition Delay Fault Patterns Considering Current Limit during Wafer Test.

Wei Zhao, Junxia Ma, Mohammad Tehranipoor, Sreejit Chakravarty

Proceedings of the 19th IEEE Asian Test Symposium, 2010

Modified Scan Flip-Flop for Low Power Testing.

Amit Mishra, Nidhi Sinha, Satdev, Virendra Singh, Sreejit Chakravarty, Adit D. Singh

Proceedings of the 19th IEEE Asian Test Symposium, 2010

2009

Fast Enhancement of Validation Test Sets for Improving the Stuck-at Fault Coverage of RTL Circuits.

Loganathan Lingappan, Vijay Gangaram, Niraj K. Jha, Sreejit Chakravarty

IEEE Trans. Very Large Scale Integr. Syst., 2009

Forecasting Stock Market Indices using Hybrid Network.

Sreejit Chakravarty, Pradipta K. Dash

Proceedings of the World Congress on Nature & Biologically Inspired Computing, 2009

Improving the Detectability of Resistive Open Faults in Scan Cells.

Fan Yang, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz

Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009

Detectability of internal bridging faults in scan chains.

Fan Yang, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz

Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

Path selection for monitoring unexpected systematic timing effects.

Nicholas Callegari, Pouria Bastani, Li-C. Wang, Sreejit Chakravarty, Alexander Tetelbaum

Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008

A Methodology for Handling Complex Functional Constraints for Large Industrial Designs.

Abhijit Jas, Yi-Shing Chang, Sreejit Chakravarty

J. Electron. Test., 2008

On the Detectability of Scan Chain Internal Faults - An Industrial Case Study.

Fan Yang, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz

Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008

An Industrial Case Study of Sticky Path-Delay Faults.

I-De Huang, Yi-Shing Chang, Sandeep K. Gupta, Sreejit Chakravarty

Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008

Detection of Internal Stuck-open Faults in Scan Chains.

Fan Yang, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz

Proceedings of the 2008 IEEE International Test Conference, 2008

An Enhanced Logic BIST Architecture for Online Testing.

Fan Yang, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz

Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008

Detection of Transistor Stuck-Open Faults in Asynchronous Inputs of Scan Cells.

Fan Yang, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz

Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008

Refining Delay Test Methodology Using Knowledge of Asymmetric Transition Delay.

Sean H. Wu, Sreejit Chakravarty, Alexander Tetelbaum, Li-C. Wang

Proceedings of the 17th IEEE Asian Test Symposium, 2008

2006

Exact Delay Fault Coverage in Sequential Logic Under Any Delay Fault Model.

Mahilchi Milir Vaseekar Kumar, Spyros Tragoudas, Sreejit Chakravarty, Rathish Jayabharathi

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Silicon Evaluation of Logic Proximity Bridge Patterns.

Eric N. Tran, Vishwashanth Kasulasrinivas, Sreejit Chakravarty

Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

Path Delay Fault Simulation on Large Industrial Designs.

Suriyaprakash Natarajan, Srinivas Patil, Sreejit Chakravarty

Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

A Study of Implication Based Pseudo Functional Testing.

Manan Syal, Kameshwar Chandrasekar, Vishnu C. Vimjam, Michael S. Hsiao, Yi-Shing Chang, Sreejit Chakravarty

Proceedings of the 2006 IEEE International Test Conference, 2006

Exact At-speed Delay Fault Grading in Sequential Circuits.

Mahilchi Milir Vaseekar Kumar, Spyros Tragoudas, Sreejit Chakravarty, Rathish Jayabharathi

Proceedings of the 2006 IEEE International Test Conference, 2006

An Approach to Minimizing Functional Constraints.

Abhijit Jas, Yi-Shing Chang, Sreejit Chakravarty

Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006

2005

Efficient techniques for transition testing.

Xiao Liu, Michael S. Hsiao, Sreejit Chakravarty, Paul J. Thadikaran

ACM Trans. Design Autom. Electr. Syst., 2005

Transition Tests for High Performance Microprocessors.

Yi-Shing Chang, Sreejit Chakravarty, Hiep Hoang, Nick Thorpe, Khen Wee

Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005

Experimental Evaluation of Bridge Patterns for a High Performance Microprocessor.

Sreejit Chakravarty, Yi-Shing Chang, Hiep Hoang, Sridhar Jayaraman, Silvio Picano, Cheryl Prunty, Eric W. Savage, Rehan Sheikh, Eric N. Tran, Khen Wee

Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005

Logic proximity bridges.

Eric N. Tran, Vamsee Krishna, Sujit T. Zachariah, Sreejit Chakravarty

Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

Implicit and Exact Path Delay Fault Grading in Sequential Circuits.

Mahilchi Milir Vaseekar Kumar, Spyros Tragoudas, Sreejit Chakravarty, Rathish Jayabharathi

Proceedings of the 2005 Design, 2005

Untestable Multi-Cycle Path Delay Faults in Industrial Designs.

Manan Syal, Michael S. Hsiao, Suriyaprakash Natarajan, Sreejit Chakravarty

Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

Improving Logic Test Quality of Microprocessors.

Sreejit Chakravarty

Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

2004

Extraction of two-node bridges from large industrial circuits.

Sujit T. Zachariah, Sreejit Chakravarty

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Identifying Untestable Transition Faults in Latch Based Designs with Multiple Clocks.

Manan Syal, Michael S. Hsiao, Sreejit Chakravarty

Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Defect Coverage Analysis of Partitioned Testing.

Sreejit Chakravarty, Eric W. Savage, Eric N. Tran

Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

2003

Algorithm to extract two-node bridges.

Sujit T. Zachariah, Sreejit Chakravarty

IEEE Trans. Very Large Scale Integr. Syst., 2003

Efficient Transition Fault ATPG Algorithms Based on Stuck-At Test Vectors.

Xiao Liu, Michael S. Hsiao, Sreejit Chakravarty, Paul J. Thadikaran

J. Electron. Test., 2003

Efficient Implication - Based Untestable Bridge Fault Identifier.

Manan Syal, Michael S. Hsiao, Kiran B. Doreswamy, Sreejit Chakravarty

Proceedings of the 21st IEEE VLSI Test Symposium (VTS 2003), 27 April, 2003

2002

Layout Analysis to Extract Open Nets Caused by Systematic Failure Mechanisms.

Sreejit Chakravarty, Kambiz Komeyli, Eric W. Savage, Michael J. Carruthers, Bret T. Stastny, Sujit T. Zachariah

Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002

Fault Models for Speed Failures Caused by Bridges and Opens.

Sreejit Chakravarty, Ankur Jain

Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002

Techniques to Reduce Data Volume and Application Time for Transition Test.

Xiao Liu, Michael S. Hsiao, Sreejit Chakravarty, Paul J. Thadikaran

Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

Experimental Evaluation of Scan Tests for Bridges.

Sreejit Chakravarty, Ankur Jain, Nandakumar Radhakrishnan, Eric W. Savage, Sujit T. Zachariah

Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

Supplemental Test Methods (Tutorial Abstract).

Sreejit Chakravarty

Proceedings of the 3rd International Symposium on Quality of Electronic Design, 2002

Novel ATPG algorithms for transition faults.

Xiao Liu, Michael S. Hsiao, Sreejit Chakravarty, Paul J. Thadikaran

Proceedings of the 7th European Test Workshop, 2002

2001

Automatic generation and compaction of March tests for memory arrays.

Kamran Zarrineh, Shambhu J. Upadhyaya, Sreejit Chakravarty

IEEE Trans. Very Large Scale Integr. Syst., 2001

Diagnostic simulation of stuck-at faults in sequential circuits using compact lists.

Ismed Hartanto, Srikanth Venkataraman, W. Kent Fuchs, Elizabeth M. Rudnick, Janak H. Patel, Sreejit Chakravarty

ACM Trans. Design Autom. Electr. Syst., 2001

A Novel Algorithm for Multi-Node Bridge Analysis of Large VLSI Circuits.

Sujit T. Zachariah, Sreejit Chakravarty

Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001

2000

STBM: a fast algorithm to simulate I_DDQ tests forleakage faults.

Sreejit Chakravarty, Sujit T. Zachariah

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

A scalable and efficient methodology to extract two node bridges from large industrial circuits.

Sujit T. Zachariah, Sreejit Chakravarty

Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

An analysis of the delay defect detection capability of the ECR test method.

Seonki Kim, Sreejit Chakravarty, Bapiraju Vinnakota

Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

A novel algorithm to extract two-node bridges.

Sujit T. Zachariah, Sreejit Chakravarty, Carl D. Roth

Proceedings of the 37th Conference on Design Automation, 2000

1999

Techniques to Encode and Compress Fault Dictionaries.

Sreejit Chakravarty, Vinodh Gopal

Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999

A Comparative Study of Pseudo Stuck-At and Leakage Fault Model.

Sujit T. Zachariah, Sreejit Chakravarty

Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

On Detecting Bridges Causing Timing Failures.

Sreenivas Mandava, Sreejit Chakravarty, Sandip Kundu

Proceedings of the IEEE International Conference On Computer Design, 1999

1998

Locating bridging faults using dynamically computed stuck-at fault dictionaries.

Yiming Gong, Sreejit Chakravarty

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

Techniques for minimizing power dissipation in scan and combinational circuits during test application.

Vinay Dabholkar, Sreejit Chakravarty, Irith Pomeranz, Sudhakar M. Reddy

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

Computing Stress Tests for Gate Oxide Shorts.

Vinay Dabholkar, Sreejit Chakravarty

Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998

A new framework for generating optimal March tests for memory arrays.

Kamran Zarrineh, Shambhu J. Upadhyaya, Sreejit Chakravarty

Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

1997

Algorithms to compute bridging fault coverage of <i>I_DDQ</i> test sets.

Paul J. Thadikaran, Sreejit Chakravarty, Janak H. Patel

ACM Trans. Design Autom. Electr. Syst., 1997

Using fault sampling to compute I_DDQ diagnostic test set.

Yiming Gong, Sreejit Chakravarty

Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997

Computing stress tests for interconnect defects.

Vinay Dabholkar, Sreejit Chakravarty

Proceedings of the 6th Asian Test Symposium (ATS '97), 17-18 November 1997, 1997

On the capability of delay tests to detect bridges and opens.

Sreejit Chakravarty

Proceedings of the 6th Asian Test Symposium (ATS '97), 17-18 November 1997, 1997

1996

Simulation and Generation of IDDQ Tests for Bridging Faults in Combinational Circuits.

Sreejit Chakravarty, Paul J. Thadikaran

IEEE Trans. Computers, 1996

A Study of Theoretical Issues in the Synthesis of Delay Fault Testability Circuits.

Sreejit Chakravarty

IEEE Trans. Computers, 1996

Algorithms to select <i>I</i>_DDQ measurement points to detect bridging faults.

Sreejit Chakravarty, Paul J. Thadikaran

J. Electron. Test., 1996

Diagnostic simulation of stuck-at faults in combinational circuits.

Sreejit Chakravarty, Yiming Gong, Srikanth Venkataraman

J. Electron. Test., 1996

A sampling technique for diagnostic fault simulation.

Sreejit Chakravarty

Proceedings of the 14th IEEE VLSI Test Symposium (VTS'96), April 28, 1996

Fast Algorithms for Computer IDDQ Tests for Combination Circuits.

Paul J. Thadikaran, Sreejit Chakravarty

Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996

1995

Conference Reports.

Sreejit Chakravarty, Ramalingam Sridhar, Shambhu J. Upadhyaya, Yervant Zorian, Gil Philips, Bozena Kaminska, Bernard Courtois

IEEE Des. Test Comput., 1995

Cyclic stress tests for full scan circuits.

Vinay Dabholkar, Sreejit Chakravarty, J. Najm, Janak H. Patel

Proceedings of the 13th IEEE VLSI Test Symposium (VTS'95), April 30, 1995

Voting model based diagnosis of bridging faults in combinational circuits.

Sreejit Chakravarty, Yiming Gong

Proceedings of the 8th International Conference on VLSI Design (VLSI Design 1995), 1995

On adaptive diagnostic test generation.

Yiming Gong, Sreejit Chakravarty

Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

Fault Simulation of<i>I_DDQ</i> Tests for Bridging Faults in Sequential Circuits.

Paul J. Thadikaran, Sreejit Chakravarty, Janak H. Patel

Proceedings of the Digest of Papers: FTCS-25, 1995

Rapid Diagnostic Fault Simulation of Stuck-at Faults in Sequential Circuits Using Compact Lists.

Srikanth Venkataraman, Ismed Hartanto, W. Kent Fuchs, Elizabeth M. Rudnick, Sreejit Chakravarty, Janak H. Patel

Proceedings of the 32st Conference on Design Automation, 1995

1994

Diagnostic simulation of stuck-at faults in combinational circuits.

Sreejit Chakravarty, Yiming Gong

Proceedings of the 12th IEEE VLSI Test Symposium (VTS'94), 1994

<i>I_DDQ</i> Measurement Based Diagnosis of Bridging Faults in Full Scan Circuits.

Sreejit Chakravarty, Sivaprakasam Suresh

Proceedings of the Seventh International Conference on VLSI Design, 1994

A Study of I_DDQ Subset Selection Algorithms for Bridging Faults.

Sreejit Chakravarty, Paul J. Thadikaran

Proceedings of the Proceedings IEEE International Test Conference 1994, 1994

1993

A Characterization of Binary Decision Diagrams.

Sreejit Chakravarty

IEEE Trans. Computers, 1993

Simulation and generation of I_DDQ tests for bridging faults in combinational circuits.

Sreejit Chakravarty, Paul J. Thadikaran

Proceedings of the 11th IEEE VLSI Test Symposium (VTS'93), 1993

An Algorithm for Diagnosing Two-Line Bridging Faults in Combinational Circuits.

Sreejit Chakravarty, Yiming Gong

Proceedings of the 30th Design Automation Conference. Dallas, 1993

1992

Parallel and serial heuristics for the minimum set cover problem.

Sreejit Chakravarty, Ajay Shekhawat

J. Supercomput., 1992

Algorithms for IDDQ measurement based diagnosis of bridging faults.

Sreejit Chakravarty, Minsheng Liu

J. Electron. Test., 1992

On Computing Tests for Bridging and Leakage Faults: Complexity Results and Universal Test Sets.

Sreejit Chakravarty

Proceedings of the Fifth International Conference on VLSI Design, 1992

Algorithms for Current Monitor Based Diagnosis of Bridging and Leakage Faults.

Sreejit Chakravarty, Minsheng Liu

Proceedings of the 29th Design Automation Conference, 1992

1991

Minimum area layout of series-parallel transistor networks is NP-hard.

Sreejit Chakravarty, Xin He, S. S. Ravi

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991

A characterization of robust test-pairs for stuck-open faults.

Sreejit Chakravarty

J. Electron. Test., 1991

1990

Computing optimal test sequences from complete test sets for stuck-open faults in CMOS circuits.

Sreejit Chakravarty, S. S. Ravi

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990

On Computing Signal Probability and Detection Probability of Stuck-at Faults.

Sreejit Chakravarty, Harry B. Hunt III

IEEE Trans. Computers, 1990

Testing of non-feedback bridging faults.

Sreejit Chakravarty

Integr., 1990

Heuristics for the MSC Problem for Serial and Shared-Memory Computers.

Ajay Shekhawat, Sreejit Chakravarty

Proceedings of the 1990 International Conference on Parallel Processing, 1990

On Synthesizing and Identifying Stuck-Open Testable CMOS Combinational Circuits (extended abstract).

Sreejit Chakravarty

Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, 1990

1989

On the complexity of computing tests for CMOS gates.

Sreejit Chakravarty

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989

The Complexity of Generating Minimum Test Sets for PLA's and Monotone Combinational Circuits.

Sreejit Chakravarty, Harry B. Hunt III, S. S. Ravi, Daniel J. Rosenkrantz

IEEE Trans. Computers, 1989

A Note on Detecting Sneak Paths in Transistor Networks.

Sreejit Chakravarty, Harry B. Hunt III

IEEE Trans. Computers, 1989

A Testable Realization of CMOS Combinational Circuits.

Sreejit Chakravarty

Proceedings of the Proceedings International Test Conference 1989, 1989

1988

A Unified Approach to Designing Fault-Tolerant Processor Ensembles.

Sreejit Chakravarty, Shambhu J. Upadhyaya

Proceedings of the International Conference on Parallel Processing, 1988

1986

On the Computation of Detection Probability for Multiple Faults.

Sreejit Chakravarty, Harry B. Hunt III

Proceedings of the Proceedings International Test Conference 1986, 1986