Warin Sootkaneung

Orcid: 0000-0002-3026-7844

According to our database1, Warin Sootkaneung authored at least 16 papers between 2008 and 2021.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Online presence:

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Bibliography

2021
Temperature-Aware Evaluation and Mitigation of Logic Soft Errors Under Circuit Variations.
Proceedings of the 30th IEEE Asian Test Symposium, 2021

2019
A Practical Technology-Enhanced Approach for Programmable Logic Controller (PLC) Training Course.
Proceedings of the ICETC 2019, 2019

2018
Temperature effects on BTI and soft errors in modern logic circuits.
Microelectron. Reliab., 2018

Implementation of Swarm Based Gain Scheduling for 2D Inverted Pendulum Using PLC.
Proceedings of the 7th International Congress on Advanced Applied Informatics, 2018

Enhancing High-School Students' Computational Thinking with Educational Robotics Learning.
Proceedings of the 7th International Congress on Advanced Applied Informatics, 2018

2017
Motivating Pre-service Teachers with Augmented Reality to Developing Instructional Materials through Project-Based Learning Approach.
Proceedings of the 6th IIAI International Congress on Advanced Applied Informatics, 2017

Thermal Effect on Performance, Power, and BTI Aging in FinFET-Based Designs.
Proceedings of the Euromicro Conference on Digital System Design, 2017

2016
Speed control technique for conveyor using PSO based PID with programmable logic controller.
Proceedings of the 2016 IEEE/SICE International Symposium on System Integration, 2016

Design and implementation of PSO based LQR control for inverted pendulum through PLC.
Proceedings of the 2016 IEEE/SICE International Symposium on System Integration, 2016

NBTI in FinFET Circuits under the Temperature Effect Inversion.
Proceedings of the 2016 IEEE Intl Conference on Computational Science and Engineering, 2016

Combined Impact of BTI and Temperature Effect Inversion on Circuit Performance.
Proceedings of the 25th IEEE Asian Test Symposium, 2016

2012
Impact of Body Bias Based Leakage Power Reduction on Soft Error Rate.
Proceedings of the 25th International Conference on VLSI Design, 2012

2011
Soft error reduction through gate input dependent weighted sizing in combinational circuits.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

2010
On techniques for handling soft errors in digital circuits.
Proceedings of the 2011 IEEE International Test Conference, 2010

Gate input reconfiguration for combating soft errors in combinational circuits.
Proceedings of the IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W 2010), Chicago, Illinois, USA, June 28, 2010

2008
NBTI Degradation: A Problem or a Scare?
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008


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