Wei-Kang Huang

According to our database1, Wei-Kang Huang authored at least 31 papers between 1988 and 2001.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2001
Novel Approaches for Fault Detection in Two-Dimensional Combinational Arrays.
Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 2001

2000
Testing and testable designs for one-time programmable FPGAs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

An Approach for Detecting Multiple Faulty FPGA Logic Blocks.
IEEE Trans. Computers, 2000

Testing programmable interconnect systems: an algorithmic approach.
Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

1999
Design Verification of FPGA Implementations.
IEEE Des. Test Comput., 1999

A Novel Fault Tolerant Approach for SRAM-Based FPGAs.
Proceedings of the 1999 Pacific Rim International Symposium on Dependable Computing (PRDC 1999), 1999

Minimizing the Number of Programming Steps for Diagnosis of Interconnect Faults in FPGAs.
Proceedings of the 8th Asian Test Symposium (ATS '99), 1999

A BIST TPG Approach for Interconnect Testing With the IEEE 1149.1 STD.
Proceedings of the 8th Asian Test Symposium (ATS '99), 1999

Diagnosing Single Faults for Interconnects in SRAM Based FPGAs.
Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999

1998
Testing configurable LUT-based FPGA's.
IEEE Trans. Very Large Scale Integr. Syst., 1998

On the Complexity of Sequential Testing in Configurable FPGAs.
Proceedings of the 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '98), 1998

A Diagnosis Method for Interconnects in SRAM Based FPGAs.
Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998

Fault Detection in a Tristate System Environment.
Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998

1997
Using Virtual Links for Reliable Information Retrieval Across Point-to-Point Networks.
Proceedings of the Digest of Papers: FTCS-27, 1997

A XOR-Tree Based Technique for Constant Testability of Configurable FPGAs.
Proceedings of the 6th Asian Test Symposium (ATS '97), 17-18 November 1997, 1997

1996
An approach for testing programmable/configurable field programmable gate arrays.
Proceedings of the 14th IEEE VLSI Test Symposium (VTS'96), April 28, 1996

On the diagnosis of programmable interconnect systems: Theory and application.
Proceedings of the 14th IEEE VLSI Test Symposium (VTS'96), April 28, 1996

Diagnosing Programmable Interconnect Systems for FPGAs.
Proceedings of the 1996 Fourth International Symposium on Field Programmable Gate Arrays, 1996

1995
Accurate communication models for task scheduling in multicomputers.
Proceedings of the Seventh IEEE Symposium on Parallel and Distributed Processing, 1995

A Submesh Allocation Scheme for Mesh-Connected Multiprocessor Systems.
Proceedings of the 1995 International Conference on Parallel Processing, 1995

A New Diagnosis Approach for Short Faults in Interconnects.
Proceedings of the Digest of Papers: FTCS-25, 1995

Testing of Uncustomized Segmented Channel Field Programmable Gate Arrays.
Proceedings of the Third International ACM Symposium on Field-Programmable Gate Arrays, 1995

A row-based FPGA for single and multiple stuck-at fault detection.
Proceedings of the 1995 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 1995

1992
Detection and Location of Multiple Faults in Baseline Interconnection Networks.
IEEE Trans. Computers, 1992

1991
Minimizing the cost of repairing WSI memories.
Integr., 1991

1990
New approaches for the repairs of memories with redundancy by row/column deletion for yield enhancement.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990

Fault Detection and Design Complextity in C-Testable VLSI Arrays.
IEEE Trans. Computers, 1990

On the Constant Diagnosability of Baseline Interconnection Networks.
IEEE Trans. Computers, 1990

1988
On an improved design approach for C-testable orthogonal iterative arrays.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988

Approaches for the repair of VLSI/WSI RRAMs by row/column deletion.
Proceedings of the Eighteenth International Symposium on Fault-Tolerant Computing, 1988

A New Two Task Algorithm for Clock Mode Fault Simulation in Sequential Circuits.
Proceedings of the 25th ACM/IEEE Conference on Design Automation, 1988


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