Yinan N. Shen

According to our database1, Yinan N. Shen authored at least 17 papers between 1989 and 1997.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

1997
On the multiple fault diagnosis of multistage interconnection networks: the lower bound and the CMOS fault model.
Proceedings of the 1997 International Conference on Parallel Processing (ICPP '97), 1997

1996
A Sweeping Line Approach to Interconnect Testing.
IEEE Trans. Computers, 1996

Graph Algorithms for Conformance Testing Using the Rural Chinese Postman Tour.
SIAM J. Discret. Math., 1996

Space Cutting Approaches for Repairing Memories.
Proceedings of the 1996 International Conference on Computer Design (ICCD '96), 1996

1994
An Approach for UIO Generation for FSM Verification and Validation.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

Scheduling Policies for Fault Tolerance in a VLSI Processor.
Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1994

1993
Fault detection in TFCMOS/DFCMOS combinational gates.
Integr., 1993

1992
Protocol conformance testing using multiple UIO sequences.
IEEE Trans. Commun., 1992

Evaluation and improvement of fault coverage of conformance testing by UIO sequences.
IEEE Trans. Commun., 1992

On the Verification and Validation of Protocols with High Fault Coverage Using UIO Sequences.
Proceedings of the 11th Symposium on Reliable Distributed Systems, 1992

1991
On a new approach for enhancing the fault coverage of conformance testing of protocols.
Proceedings of the Third IEEE Symposium on Parallel and Distributed Processing, 1991

Protocol Conformance Testing by Discriminating UIO Sequences.
Proceedings of the Protocol Specification, 1991

1990
New approaches for the repairs of memories with redundancy by row/column deletion for yield enhancement.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990

Yield enhancement and manufacturing throughput of redundant memories by repairability/unrepairability detection.
J. Electron. Test., 1990

Evaluation and improvement of fault coverage for verification and validation of protocols.
Proceedings of the Second IEEE Symposium on Parallel and Distributed Processing, 1990

On the testability of array structures for FFT computation.
Proceedings of the Second IEEE Symposium on Parallel and Distributed Processing, 1990

1989
Location and Identification for Single and Multiple Faults in Testable Redundant PLAs for Yield Enhancement.
Proceedings of the Proceedings International Test Conference 1989, 1989


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