Fred J. Meyer

According to our database1, Fred J. Meyer authored at least 55 papers between 1988 and 2006.

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Bibliography

2006
Measuring the timing jitter of ATE in the frequency domain.
IEEE Trans. Instrum. Meas., 2006

Evaluating the Yield of Repairable SRAMs for ATE.
IEEE Trans. Instrum. Meas., 2006

2005
Analysis and evaluation of multisite testing for VLSI.
IEEE Trans. Instrum. Meas., 2005

QCA-Based Majority Gate Design under Radius of Effect-Induced Faults.
Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005

2004
Sequential diagnosis of processor array systems.
IEEE Trans. Reliab., 2004

Analysis and measurement of fault coverage in a combined ATE and BIST environment.
IEEE Trans. Instrum. Meas., 2004

Guest editorial.
J. Syst. Archit., 2004

Simulation of reconfigurable memory core yield.
Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004

On The Yield of Compiler-Based eSRAMs.
Proceedings of the 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 2004

Reliability Modeling and Assurance of Clockless Wave Pipeline.
Proceedings of the 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 2004

2003
Maximal diagnosis of interconnects of random access memories.
IEEE Trans. Reliab., 2003

Analysis and measurement of timing jitter induced by radiated EMI noise in automatic test equipment.
IEEE Trans. Instrum. Meas., 2003

Predicting Defect-Tolerant Yield in the Embedded Core Context.
IEEE Trans. Computers, 2003

Adaptive Algorithms for Maximal Diagnosis of Wiring Interconnects.
IEEE Trans. Computers, 2003

Hybrid Multisite Testing at Manufacturing.
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

A Digital and Wide Power Bandwidth H-Field Generator for Automatic Test Equipment.
Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003

2002
Quality-effective repair of multichip module systems.
J. Syst. Archit., 2002

Analyzing and Diagnosing Interconnect Faults in Bus-Structured Systems.
IEEE Des. Test Comput., 2002

Random Testing of Multi-Port Static Random Access Memories.
Proceedings of the 10th IEEE International Workshop on Memory Technology, 2002

Test Time Reduction in a Manufacturing Environment by Combining BIST and ATE.
Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 2002

2001
Connectivity-Based Multichip Module Repair.
Proceedings of the 8th Pacific Rim International Symposium on Dependable Computing (PRDC 2001), 2001

Novel Approaches for Fault Detection in Two-Dimensional Combinational Arrays.
Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 2001

2000
Testing and testable designs for one-time programmable FPGAs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

An Approach for Detecting Multiple Faulty FPGA Logic Blocks.
IEEE Trans. Computers, 2000

Diagnosing the Interconnect of Bus-Connected Multi-RAM Systems under Restricted and General Fault Models.
Proceedings of the 8th IEEE International Workshop on Memory Technology, 2000

Complexity Bounds for Lookup Table Implementation of Factored Forms in FPGA Technology Mapping.
Proceedings of the Parallel and Distributed Processing, 2000

1999
Test generation and scheduling for layout-based detection of bridge faults in interconnects.
IEEE Trans. Very Large Scale Integr. Syst., 1999

Reconfiguring one-time programmable FPGAs.
IEEE Micro, 1999

Adaptive Fault Detection and Diagnosis of RAM Interconnects.
J. Electron. Test., 1999

Guest Editors' Introduction: DRAM Architecture and Testing.
IEEE Des. Test Comput., 1999

Design Verification of FPGA Implementations.
IEEE Des. Test Comput., 1999

Maximal Diagnosis of Interconnects of Random Access Memories.
Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999

Interconnect Diagnosis of Bus-Connected Multi-RAM Systems.
Proceedings of the 7th IEEE International Workshop on Memory Technology, 1999

Two-Step Algorithms for Maximal Diagnosis of Wiring Interconnects.
Proceedings of the Digest of Papers: FTCS-29, 1999

Good Processor Identification in Two-Dimensional Grids.
Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '99), 1999

Novel Control Pattern Generators for Interconnect Testing with Boundary Scan.
Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '99), 1999

Reconfiguration of One-Time Programmable FPGAs with Faulty Logic Resources.
Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '99), 1999

A BIST TPG Approach for Interconnect Testing With the IEEE 1149.1 STD.
Proceedings of the 8th Asian Test Symposium (ATS '99), 1999

1998
Testing configurable LUT-based FPGA's.
IEEE Trans. Very Large Scale Integr. Syst., 1998

Structural diagnosis of interconnects by coloring.
ACM Trans. Design Autom. Electr. Syst., 1998

Fault Detection and Diagnosis of Interconnects of Random Access Memories.
Proceedings of the 16th IEEE VLSI Test Symposium (VTS '98), 28 April, 1998

A New Method for Testing EEPLA's.
Proceedings of the 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '98), 1998

On the Complexity of Sequential Testing in Configurable FPGAs.
Proceedings of the 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '98), 1998

Fault Detection in a Tristate System Environment.
Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998

1997
On the Fault Coverage of Interconnect Diagnosis.
Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997

Using Virtual Links for Reliable Information Retrieval Across Point-to-Point Networks.
Proceedings of the Digest of Papers: FTCS-27, 1997

Multiple fault detection in logic resources of FPGAs.
Proceedings of the 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems (DFT '97), 1997

Testing of programmable logic devices (PLD) with faulty resources.
Proceedings of the 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems (DFT '97), 1997

A XOR-Tree Based Technique for Constant Testability of Configurable FPGAs.
Proceedings of the 6th Asian Test Symposium (ATS '97), 17-18 November 1997, 1997

1993
Yield optimization of modular and redundant multimegabit RAMs: a study of effectiveness of coding versus static redundancy using the center-satellite model.
IEEE Trans. Very Large Scale Integr. Syst., 1993

Communication structures in fault-tolerant distributed systems.
Networks, 1993

1991
Consensus With Dual Failure Modes.
IEEE Trans. Parallel Distributed Syst., 1991

1989
Modeling Defect Spatial Distribution.
IEEE Trans. Computers, 1989

Dynamic Testing Strategy for Distributed Systems.
IEEE Trans. Computers, 1989

1988
Flip-Trees: Fault-Tolerant Graphs with Wide Containers.
IEEE Trans. Computers, 1988


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