Wei Wang
Orcid: 0000-0001-5804-0230Affiliations:
- University of Macau, State Key Laboratory of Analog and Mixed-Signal VLSI, Macau
According to our database1,
Wei Wang
authored at least 8 papers
between 2014 and 2022.
Collaborative distances:
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Bibliography
2022
A Single-Opamp Third Order CT ΔΣ Modulator With SAB-ELD-Merged Integrator and Three-Stage Hybrid Compensation Opamp.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
2020
A 100-MHz BW 72.6-dB-SNDR CT ΔΣ Modulator Utilizing Preliminary Sampling and Quantization.
IEEE J. Solid State Circuits, 2020
A 10.4mW 50MHz-BW 80dB-DR Single-Opamp Third-Order CTSDM with SAB-ELD-Merged Integrator and 3-Stage Opamp.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
2019
A 72.6dB-SNDR 100MHz-BW 16.36mW CTDSM with Preliminary Sampling and Quantization Scheme in Backend Subranging QTZ.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
2018
A 5.35-mW 10-MHz Single-Opamp Third-Order CT ΔΣ Modulator With CTC Amplifier and Adaptive Latch DAC Driver in 65-nm CMOS.
IEEE J. Solid State Circuits, 2018
2017
A 5.35 mW 10 MHz bandwidth CT third-order ΔΣ modulator with single Opamp achieving 79.6/84.5 dB SNDR/DR in 65 nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017
2015
A 0.0045-mm<sup>2</sup> 32.4-µW Two-Stage Amplifier for pF-to-nF Load Using CM Frequency Compensation.
IEEE Trans. Circuits Syst. II Express Briefs, 2015
2014
Micropower two-stage amplifier employing recycling current-buffer Miller compensation.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014