Wei Xu

Affiliations:
  • Marvell Technology, Santa Clara, CA, USA (since 2009)
  • Rensselaer Polytechnic Institute, Electrical and Computer Science Engineering Department, Troy, NY, USA (PhD 2009)


According to our database1, Wei Xu authored at least 13 papers between 2008 and 2013.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2013
Exploring the Use of Emerging Nonvolatile Memory Technologies in Future FPGAs.
IEEE Trans. Very Large Scale Integr. Syst., 2013

Using Multilevel Phase Change Memory to Build Data Storage: A Time-Aware System Design Perspective.
IEEE Trans. Computers, 2013

2012
Using Magnetic RAM to Build Low-Power and Soft Error-Resilient L1 Cache.
IEEE Trans. Very Large Scale Integr. Syst., 2012

A 130 nm 1.2 V/3.3 V 16 Kb Spin-Transfer Torque Random Access Memory With Nondestructive Self-Reference Sensing Scheme.
IEEE J. Solid State Circuits, 2012

2011
A Time-Aware Fault Tolerance Scheme to Improve Reliability of Multilevel Phase-Change Memory in the Presence of Significant Resistance Drift.
IEEE Trans. Very Large Scale Integr. Syst., 2011

Design of Last-Level On-Chip Cache Using Spin-Torque Transfer RAM (STT RAM).
IEEE Trans. Very Large Scale Integr. Syst., 2011

2010
Design of Spin-Torque Transfer Magnetoresistive RAM and CAM/TCAM with High Sensing and Search Speed.
IEEE Trans. Very Large Scale Integr. Syst., 2010

Using time-aware memory sensing to address resistance drift issue in multi-level phase change memory.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

Combined magnetic- and circuit-level enhancements for the nondestructive self-reference scheme of STT-RAM.
Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010

A nondestructive self-reference scheme for Spin-Transfer Torque Random Access Memory (STT-RAM).
Proceedings of the Design, Automation and Test in Europe, 2010

2009
Data manipulation techniques to reduce phase change memory write energy.
Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009

Improving STT MRAM storage density through smaller-than-worst-case transistor sizing.
Proceedings of the 46th Design Automation Conference, 2009

2008
Spin-transfer torque magnetoresistive content addressable memory (CAM) cell structure design with enhanced search noise margin.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008


  Loading...