Wei Yuan

Orcid: 0000-0001-9357-5716

According to our database1, Wei Yuan authored at least 11 papers between 2021 and 2025.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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Bibliography

2025
FANNS: An FPGA-Based Approximate Nearest-Neighbor Search Accelerator.
IEEE Trans. Very Large Scale Integr. Syst., April, 2025

GHVSA: Graph-based high-dimensional vector search accelerator.
J. Syst. Archit., 2025

Exploring the Performance Improvement of Tensor Processing Engines through Transformation in the Bit-weight Dimension of MACs.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2025

2024
HBM-Based Hardware Accelerator for GNN Sampling and Aggregation.
Proceedings of the IEEE High Performance Extreme Computing Conference, 2024

RingTK: A Ring, Parallel and High Performance Top-K Sorter on FPGA.
Proceedings of the 32nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2024

A FPGA-HBM-Based Hardware Streaming Accelerator for GNN Sampling.
Proceedings of the 35th IEEE International Conference on Application-specific Systems, 2024

2022
QEGCN: An FPGA-based accelerator for quantized GCNs with edge-level parallelism.
J. Syst. Archit., 2022

FP-GNN: Adaptive FPGA accelerator for Graph Neural Networks.
Future Gener. Comput. Syst., 2022

Hardware Acceleration of Sampling Algorithms in Sample and Aggregate Graph Neural Networks.
CoRR, 2022

2021
A Gather Accelerator for GNNs on FPGA Platform.
Proceedings of the 27th IEEE International Conference on Parallel and Distributed Systems, 2021

Software-Hardware Co-Optimization on Partial-Sum Problem for PIM-based Neural Network Accelerator.
Proceedings of the 2021 IEEE High Performance Extreme Computing Conference, 2021


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