Xi Jin

Orcid: 0000-0002-4159-2925

Affiliations:

University of Science and Technology of China, State Key Laboratory of Particle Detection and Electronics, Institute of Microelectronics, Department of Physics, SoC Lab, Hefei, China

According to our database¹, Xi Jin authored at least 46 papers between 2014 and 2024.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

Legend:

Book

In proceedings

Article

PhD thesis

Dataset

Other

Bibliography

2024

Efficient Message Passing Architecture for GCN Training on HBM-based FPGAs with Orthogonal Topology On-Chip Networks.

[BibT_eX]

[DOI]

Proceedings of the 2024 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2024

2023

FTW-GAT: An FPGA-Based Accelerator for Graph Attention Networks With Ternary Weights.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, November, 2023

Degree-Aware Graph Neural Network Quantization.

[BibT_eX]

[DOI]

Ziqin Fan

Xi Jin

Entropy, November, 2023

MCANet: Multiscale Cross-Modality Attention Network for Multispectral Pedestrian Detection.

[BibT_eX]

[DOI]

Proceedings of the MultiMedia Modeling - 29th International Conference, 2023

Scheduling Memory Access Optimization for HBM Based on CLOS.

[BibT_eX]

[DOI]

Proceedings of the 25th International Conference on Advanced Communication Technology, 2023

Dynamic Neural Network Accelerator for Multispectral detection Based on FPGA.

[BibT_eX]

[DOI]

Proceedings of the 25th International Conference on Advanced Communication Technology, 2023

2022

Exploration of Balanced Design in Resource-Constrained Edge Device for Efficient CNNs.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2022

BaPipe: Balanced Pipeline Parallelism for DNN Training.

[BibT_eX]

[DOI]

Parallel Process. Lett., 2022

QEGCN: An FPGA-based accelerator for quantized GCNs with edge-level parallelism.

[BibT_eX]

[DOI]

J. Syst. Archit., 2022

G-NMP: Accelerating Graph Neural Networks with DIMM-based Near-Memory Processing.

[BibT_eX]

[DOI]

J. Syst. Archit., 2022

FP-GNN: Adaptive FPGA accelerator for Graph Neural Networks.

[BibT_eX]

[DOI]

Future Gener. Comput. Syst., 2022

Hardware Acceleration of Sampling Algorithms in Sample and Aggregate Graph Neural Networks.

[BibT_eX]

[DOI]

CoRR, 2022

HuGraph: Acceleration of GCN Training on Heterogeneous FPGA Clusters with Quantization.

[BibT_eX]

[DOI]

Proceedings of the IEEE High Performance Extreme Computing Conference, 2022

An SSD-Based Accelerator for Singular Value Decomposition Recommendation Algorithm on Edge.

[BibT_eX]

[DOI]

Proceedings of the IEEE High Performance Extreme Computing Conference, 2022

2021

A hybrid precision low power computing-in-memory architecture for neural networks.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2021

A Gather Accelerator for GNNs on FPGA Platform.

[BibT_eX]

[DOI]

Proceedings of the 27th IEEE International Conference on Parallel and Distributed Systems, 2021

Software-Hardware Co-Optimization on Partial-Sum Problem for PIM-based Neural Network Accelerator.

[BibT_eX]

[DOI]

Proceedings of the 2021 IEEE High Performance Extreme Computing Conference, 2021

2020

FPDeep: Scalable Acceleration of CNN Training on Deeply-Pipelined FPGA Clusters.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2020

A Real-Time Learning-Based Super-Resolution System on FPGA.

[BibT_eX]

[DOI]

Parallel Process. Lett., 2020

Enhancing energy efficiency of RISC-V processor-based embedded graphics systems through frame buffer compression.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2020

FPGA Implementation of A∗ Algorithm for Real-Time Path Planning.

[BibT_eX]

[DOI]

Yuzhi Zhou

Xi Jin

Tianqi Wang

Int. J. Reconfigurable Comput., 2020

BaPipe: Exploration of Balanced Pipeline Parallelism for DNN Training.

[BibT_eX]

[DOI]

CoRR, 2020

TB-DNN: A Thin Binarized Deep Neural Network with High Accuracy.

[BibT_eX]

[DOI]

Jie Wang

Xi Jin

Wei Wu

Proceedings of the 22nd International Conference on Advanced Communication Technology, 2020

Exploration of Memory Access Optimization for FPGA-based 3D CNN Accelerator.

[BibT_eX]

[DOI]

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

RISC-V Graphics Rendering Instruction Set Extensions for Embedded AI Chips Implementation.

[BibT_eX]

[DOI]

Yuzhi Zhou

Xi Jin

Tian Xiang

Proceedings of the BDET 2020: 2nd International Conference on Big Data Engineering and Technology, 2020

2019

A Scalable Framework for Acceleration of CNN Training on Deeply-Pipelined FPGA Clusters with Weight and Workload Balancing.

[BibT_eX]

[DOI]

CoRR, 2019

CINT - An Energy-efficient Mixed-signal In-Memory CNN Accelerator Based on NOR Flash Memory.

[BibT_eX]

[DOI]

Proceedings of the 17th Annual International Conference on Mobile Systems, 2019

FP-AMR: A Reconfigurable Fabric Framework for Adaptive Mesh Refinement Applications.

[BibT_eX]

[DOI]

Proceedings of the 27th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2019

Accelerating AP3M-Based Computational Astrophysics Simulations with Reconfigurable Clusters.

[BibT_eX]

[DOI]

Proceedings of the 30th IEEE International Conference on Application-specific Systems, 2019

2018

RP-Ring: A Heterogeneous Multi-FPGA Accelerator.

[BibT_eX]

[DOI]

Int. J. Reconfigurable Comput., 2018

A pipelined division for fixed operation using user-defined floating point.

[BibT_eX]

[DOI]

Pengfei Yang

Daolu Zha

Xi Jin

Proceedings of the 20th International Conference on Advanced Communication Technology, 2018

Accelerating a radio astronomy correlator on FPGA.

[BibT_eX]

[DOI]

Shuaizhi Guo

Linlin Zheng

Xi Jin

Proceedings of the 20th International Conference on Advanced Communication Technology, 2018

Soft-Core. Multiple-Lane, FPGA-based ADCs for a Liquid Helium Environment.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE High Performance Extreme Computing Conference, 2018

An efficient resource-optimized learning prefetcher for solid state drives.

[BibT_eX]

[DOI]

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

A Real-Time Learning-Based Super-Resolution System Using Direct Simple Functions.

[BibT_eX]

[DOI]

Proceedings of the 29th IEEE International Conference on Application-specific Systems, 2018

2017

An Efficient Hardware Prefetcher Exploiting the Prefetch Potential of Long-Stride Access Pattern on Virtual Address.

[BibT_eX]

[DOI]

Teng Tian

Tianqi Wang

Xi Jin

Proceedings of the 2017 IEEE International Symposium on Parallel and Distributed Processing with Applications and 2017 IEEE International Conference on Ubiquitous Computing and Communications (ISPA/IUCC), 2017

2016

A real-time global stereo-matching on FPGA.

[BibT_eX]

[DOI]

Daolu Zha

Xi Jin

Tian Xiang

Microprocess. Microsystems, 2016

An Accelerating Solution for N-Body MOND Simulation with FPGA-SoC.

[BibT_eX]

[DOI]

Bo Peng