We stand with Ukraine

We stand with Ukraine

Wei Zhang

Orcid: 0000-0001-9405-447X

Affiliations:

University of Virginia, Charlottesville, VA, USA
City University of Hong Kong, Department of Electronic Engineering, Hong Kong (former)

According to our database¹, Wei Zhang authored at least 17 papers between 2011 and 2026.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

Legend:

Book In proceedings Article PhD thesis Dataset Other

Links

Online presence:

On csauthors.net:

Bibliography

2026

FIITED: Fine-Grained Embedding Dimension Optimization During Training for Recommender Systems.

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IEEE Trans. Computers, February, 2026

PackInfer: Compute- and I/O-Efficient Attention for Batched LLM Inference.

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CoRR, February, 2026

JITServe: SLO-aware LLM Serving with Imprecise Request Information.

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Proceedings of the 23rd USENIX Symposium on Networked Systems Design and Implementation, 2026

2025

Tempo: Application-aware LLM Serving with Mixed SLO Requirements.

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CoRR, April, 2025

2024

Fine-Grained Embedding Dimension Optimization During Training for Recommender Systems.

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CoRR, 2024

2023

AdaEmbed: Adaptive Embedding for Large-Scale Recommendation Models.

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Chun-cheng Jason Chen

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Mosharaf Chowdhury

Proceedings of the 17th USENIX Symposium on Operating Systems Design and Implementation, 2023

2021

Extending Performance-Energy Trade-offs Via Dynamic Core Scaling.

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IEEE Trans. Computers, 2021

2015

Reducing dynamic energy of set-associative L1 instruction cache by early tag lookup.

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Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015

Dynamic core scaling: Trading off performance and energy beyond DVFS.

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Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

2014

Adaptive front-end throttling for superscalar processors.

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Proceedings of the International Symposium on Low Power Electronics and Design, 2014

A low-power accuracy-configurable floating point multiplier.

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Proceedings of the 32nd IEEE International Conference on Computer Design, 2014

2013

Sensing nanosecond-scale voltage attacks and natural transients in FPGAs.

[DOI]

Kenneth M. Zick

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Meeta Srivastav

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Proceedings of the 2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2013

2011

High-Performance and Scalable System Architecture for the Real-Time Estimation of Generalized Laguerre-Volterra MIMO Model From Neural Population Spiking Activity.

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Rosa H. M. Chan

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Ray C. C. Cheung

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Theodore W. Berger

IEEE J. Emerg. Sel. Topics Circuits Syst., 2011

Rapid single-chip secure processor prototyping on the OpenSPARC FPGA platform.

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David Champagne

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Ray C. C. Cheung

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Proceedings of the 22nd IEEE International Symposium on Rapid System Prototyping, 2011

FPGA Architecture of Generalized Laguerre-Volterra MIMO Model for Neural Population Activities.

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Rosa H. M. Chan

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Ray C. C. Cheung

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Theodore W. Berger

Proceedings of the International Conference on Field Programmable Logic and Applications, 2011

FPGA Architecture of Generalized Laguerre-Volterra MIMO Model for Neural Population Spiking Activities.

[DOI]

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Ray C. C. Cheung

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Rosa H. M. Chan

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Theodore W. Berger

Proceedings of the IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines, 2011

A hardware-based computational platform for Generalized Laguerre-Volterra MIMO model for neural activities.

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Rosa H. M. Chan

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Ray C. C. Cheung

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Theodore W. Berger

Proceedings of the 33rd Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2011

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