Weihang Tan

According to our database, Weihang Tan authored at least 12 papers between 2019 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of three.

2024

PaReNTT: Low-Latency Parallel Residue Number System and NTT-Based Long Polynomial Modular Multiplication for Homomorphic Encryption.

Weihang Tan, Sin-Wei Chiu, Antian Wang, Yingjie Lao, Keshab K. Parhi

IEEE Trans. Inf. Forensics Secur., 2024

2023

High-Speed VLSI Architectures for Modular Polynomial Multiplication via Fast Filtering and Applications to Lattice-Based Cryptography.

Weihang Tan, Antian Wang, Xinmiao Zhang, Yingjie Lao, Keshab K. Parhi

IEEE Trans. Computers, September, 2023

KyberMat: Efficient Accelerator for Matrix-Vector Polynomial Multiplication in CRYSTALS-Kyber Scheme via NTT and Polyphase Decomposition.

Weihang Tan, Yingjie Lao, Keshab K. Parhi

Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

NNTesting: Neural Network Fault Attacks Detection Using Gradient-Based Test Vector Generation.

Antian Wang, Bingyin Zhao, Weihang Tan, Yingjie Lao

Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

2022

Integral Sampler and Polynomial Multiplication Architecture for Lattice-based Cryptography.

Antian Wang, Weihang Tan, Keshab K. Parhi, Yingjie Lao

Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2022

2021

An Ultra-Highly Parallel Polynomial Multiplier for the Bootstrapping Algorithm in a Fully Homomorphic Encryption Scheme.

Weihang Tan, Benjamin M. Case, Gengran Hu, Shuhong Gao, Yingjie Lao

J. Signal Process. Syst., 2021

High-Speed Modular Multiplier for Lattice-Based Cryptosystems.

Weihang Tan, Benjamin M. Case, Antian Wang, Shuhong Gao, Yingjie Lao

IEEE Trans. Circuits Syst. II Express Briefs, 2021

NoPUF: A Novel PUF Design Framework Toward Modeling Attack Resistant PUFs.

Antian Wang, Weihang Tan, Yuejiang Wen, Yingjie Lao

IEEE Trans. Circuits Syst. I Regul. Pap., 2021

Low-Latency VLSI Architectures for Modular Polynomial Multiplication via Fast Filtering and Applications to Lattice-Based Cryptography.

Weihang Tan, Antian Wang, Yingjie Lao, Xinmiao Zhang, Keshab K. Parhi

CoRR, 2021

Pipelined High-Throughput NTT Architecture for Lattice-Based Cryptography.

Weihang Tan, Antian Wang, Yingjie Lao, Xinmiao Zhang, Keshab K. Parhi

Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2021

2020

Area-Efficient Pipelined VLSI Architecture for Polar Decoder.

Weihang Tan, Antian Wang, Yunhao Xu, Yingjie Lao

Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020

2019

An Efficient Polynomial Multiplier Architecture for the Bootstrapping Algorithm in a Fully Homomorphic Encryption Scheme.

Weihang Tan, Aengran Au, Benjamin Aase, Shuhong Aao, Yingjie Lao

Proceedings of the 2019 IEEE International Workshop on Signal Processing Systems, 2019