Yingjie Lao

Orcid: 0000-0002-9413-2455

According to our database1, Yingjie Lao authored at least 73 papers between 2013 and 2024.

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Bibliography

2024
Reliable Hardware Watermarks for Deep Learning Systems.
IEEE Trans. Very Large Scale Integr. Syst., April, 2024

PaReNTT: Low-Latency Parallel Residue Number System and NTT-Based Long Polynomial Modular Multiplication for Homomorphic Encryption.
IEEE Trans. Inf. Forensics Secur., 2024

Resource Efficient Deep Learning Hardware Watermarks with Signature Alignment.
Proceedings of the Thirty-Eighth AAAI Conference on Artificial Intelligence, 2024

2023
Data-Driven Feature Selection Framework for Approximate Circuit Design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2023

High-Speed VLSI Architectures for Modular Polynomial Multiplication via Fast Filtering and Applications to Lattice-Based Cryptography.
IEEE Trans. Computers, September, 2023

Deep Neural Network Quantization Framework for Effective Defense against Membership Inference Attacks.
Sensors, September, 2023

UltraClean: A Simple Framework to Train Robust Neural Networks against Backdoor Attacks.
CoRR, 2023

Understanding the Robustness of Randomized Feature Defense Against Query-Based Adversarial Attacks.
CoRR, 2023

Machine Unlearning in Gradient Boosting Decision Trees.
Proceedings of the 29th ACM SIGKDD Conference on Knowledge Discovery and Data Mining, 2023

Fully Attentional Networks with Self-emerging Token Labeling.
Proceedings of the IEEE/CVF International Conference on Computer Vision, 2023

KyberMat: Efficient Accelerator for Matrix-Vector Polynomial Multiplication in CRYSTALS-Kyber Scheme via NTT and Polyphase Decomposition.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

NNTesting: Neural Network Fault Attacks Detection Using Gradient-Based Test Vector Generation.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

Sailfish: A Dependency-Aware and Resource Efficient Scheduling for Low Latency in Clouds.
Proceedings of the IEEE International Conference on Big Data, 2023

Homomorphic Evaluation Friendly Vision Transformer Design.
Proceedings of the 57th Asilomar Conference on Signals, Systems, and Computers, ACSSC 2023, Pacific Grove, CA, USA, October 29, 2023

Defending Backdoor Attacks on Vision Transformer via Patch Processing.
Proceedings of the Thirty-Seventh AAAI Conference on Artificial Intelligence, 2023

2022
Hardware Acceleration for Postdecision State Reinforcement Learning in IoT Systems.
IEEE Internet Things J., 2022

Towards Class-Oriented Poisoning Attacks Against Neural Networks.
Proceedings of the IEEE/CVF Winter Conference on Applications of Computer Vision, 2022

Marksman Backdoor: Backdoor Attacks with Arbitrary Target Class.
Proceedings of the Advances in Neural Information Processing Systems 35: Annual Conference on Neural Information Processing Systems 2022, 2022

Integrity Authentication in Tree Models.
Proceedings of the KDD '22: The 28th ACM SIGKDD Conference on Knowledge Discovery and Data Mining, Washington, DC, USA, August 14, 2022

Genetic-based Joint Dynamic Pruning and Learning Algorithm to Boost DNN Performance.
Proceedings of the 26th International Conference on Pattern Recognition, 2022

Towards Model Quantization on the Resilience Against Membership Inference Attacks.
Proceedings of the 2022 IEEE International Conference on Image Processing, 2022

Identification for Deep Neural Network: Simply Adjusting Few Weights!
Proceedings of the 38th IEEE International Conference on Data Engineering, 2022

In Pursuit of Preserving the Fidelity of Adversarial Images.
Proceedings of the IEEE International Conference on Acoustics, 2022

Integral Sampler and Polynomial Multiplication Architecture for Lattice-based Cryptography.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2022

NL2GDPR: Automatically Develop GDPR Compliant Android Application Features from Natural Language.
Proceedings of the 10th IEEE Conference on Communications and Network Security, 2022

CLPA: Clean-Label Poisoning Availability Attacks Using Generative Adversarial Nets.
Proceedings of the Thirty-Sixth AAAI Conference on Artificial Intelligence, 2022

DeepAuth: A DNN Authentication Framework by Model-Unique and Fragile Signature Embedding.
Proceedings of the Thirty-Sixth AAAI Conference on Artificial Intelligence, 2022

DeepHardMark: Towards Watermarking Neural Network Hardware.
Proceedings of the Thirty-Sixth AAAI Conference on Artificial Intelligence, 2022

2021
An Ultra-Highly Parallel Polynomial Multiplier for the Bootstrapping Algorithm in a Fully Homomorphic Encryption Scheme.
J. Signal Process. Syst., 2021

High-Speed Modular Multiplier for Lattice-Based Cryptosystems.
IEEE Trans. Circuits Syst. II Express Briefs, 2021

NoPUF: A Novel PUF Design Framework Toward Modeling Attack Resistant PUFs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

Low-Latency VLSI Architectures for Modular Polynomial Multiplication via Fast Filtering and Applications to Lattice-Based Cryptography.
CoRR, 2021

Rallying Adversarial Techniques against Deep Learning for Network Security.
Proceedings of the IEEE Symposium Series on Computational Intelligence, 2021

Backdoor Attack with Imperceptible Input and Latent Modification.
Proceedings of the Advances in Neural Information Processing Systems 34: Annual Conference on Neural Information Processing Systems 2021, 2021

Robust Watermarking for Deep Neural Networks via Bi-level Optimization.
Proceedings of the 2021 IEEE/CVF International Conference on Computer Vision, 2021

LIRA: Learnable, Imperceptible and Robust Backdoor Attacks.
Proceedings of the 2021 IEEE/CVF International Conference on Computer Vision, 2021

Pipelined High-Throughput NTT Architecture for Lattice-Based Cryptography.
Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2021

2020
Mathematical Modeling Analysis of Strong Physical Unclonable Functions.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Class-Oriented Poisoning Attack.
CoRR, 2020

Area-Efficient Pipelined VLSI Architecture for Polar Decoder.
Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020

Action Evaluation Hardware Accelerator for Next-Generation Real-Time Reinforcement Learning in Emerging IoT Systems.
Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020

2019
On the Construction of Composite Finite Fields for Hardware Obfuscation.
IEEE Trans. Computers, 2019

An Efficient Polynomial Multiplier Architecture for the Bootstrapping Algorithm in a Fully Homomorphic Encryption Scheme.
Proceedings of the 2019 IEEE International Workshop on Signal Processing Systems, 2019

Towards Data-Driven Approximate Circuit Design.
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

Hardware Obfuscation Through Reconfiguration Finite Field Arithmetic Units.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Hardware Trojan Design on Neural Networks.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Security Analysis and Modeling Attacks on Duty Cycle Multiplexer PUF.
Proceedings of the 13th IEEE International Conference on ASIC, 2019

2018
Canonic Composite Length Real-Valued FFT.
J. Signal Process. Syst., 2018

Hardware Trojan Attacks on Neural Networks.
CoRR, 2018

Efficient PUF Error Correction through Response Weighting.
Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018

Utilizing Inherent Randomness in Stochastic Computing.
Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018

Resilience of Pruned Neural Network Against Poisoning Attack.
Proceedings of the 13th International Conference on Malicious and Unwanted Software, 2018

PUF Modeling Attack using Active Learning.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

A Systematic Method for Approximate Circuit Design Using Feature Selection.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Backdoor Attacks on Neural Network Operations.
Proceedings of the 2018 IEEE Global Conference on Signal and Information Processing, 2018

A New Error Correction Scheme for Physical Unclonable Function.
Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018

2017
Reliable PUF-Based Local Authentication With Self-Correction.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Canonic FFT flow graphs for real-valued even/odd symmetric inputs.
EURASIP J. Adv. Signal Process., 2017

Efficient fuzzy extractor implementations for PUF based authentication.
Proceedings of the 12th International Conference on Malicious and Unwanted Software, 2017

Enhancing PUF reliability by machine learning.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

DC MUX PUF: A highly reliable feed-back MUX PUF based on measuring duty cycle.
Proceedings of the 12th IEEE International Conference on ASIC, 2017

2016
Beat Frequency Detector-Based High-Speed True Random Number Generators: Statistical Modeling and Analysis.
ACM J. Emerg. Technol. Comput. Syst., 2016

Data-Canonic Real FFT Flow-Graphs for Composite Lengths.
Proceedings of the 2016 IEEE International Workshop on Signal Processing Systems, 2016

Soft Response Generation and Thresholding Strategies for Linear and Feed-Forward MUX PUFs.
Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016

Estimating delay differences of arbiter PUFs using silicon data.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015
Obfuscating DSP Circuits via High-Level Transformations.
IEEE Trans. Very Large Scale Integr. Syst., 2015

An obfuscated radix-2 real FFT architecture.
Proceedings of the 2015 IEEE International Conference on Acoustics, 2015

Canonic real-valued radix-2n FFT computations.
Proceedings of the 49th Asilomar Conference on Signals, Systems and Computers, 2015

2014
Statistical Analysis of MUX-Based Physical Unclonable Functions.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Protecting DSP circuits through obfuscation.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

True Random Number Generator circuits based on single- and multi-phase beat frequency detection.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

Canonic real-valued FFT structures.
Proceedings of the 48th Asilomar Conference on Signals, Systems and Computers, 2014

2013
An In-Place FFT Architecture for Real-Valued Signals.
IEEE Trans. Circuits Syst. II Express Briefs, 2013


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