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Weijie Jiang

Orcid: 0009-0003-2465-9336

According to our database1, Weijie Jiang authored at least 3 papers between 2023 and 2025.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

Online presence:

On csauthors.net:

Bibliography

2025
HUNBN, a 16-nm Digital In-Memory-Compute SoC for Edge CNN Application Achieving 24 TOPs/W (4b) at System Level.
[BibTeX]
[DOI]
Weijie Jiang
,
Cédric Caron
,
Prabhat Avasare
,
Marc Pauwels
,
Marian Verhelst
,
Wim Dehaene
IEEE J. Solid State Circuits, July, 2025

CIPL: A Fast and Low-Power Level Shifter for Wide-Range Voltage Conversion.
[BibTeX]
[DOI]
Weijie Jiang
,
Xinfa Zheng
,
Jiacong Sun
,
Georges G. E. Gielen
,
Marian Verhelst
,
Wim Dehaene
Proceedings of the IEEE International Symposium on Circuits and Systems, 2025

2023
A 16nm 128kB high-density fully digital In Memory Compute macro with reverse SRAM pre-charge achieving 0.36TOPs/mm<sup>2</sup>, 256kB/mm<sup>2</sup> and 23. 8TOPs/W.
[BibTeX]
[DOI]
Weijie Jiang
,
Pouya Houshmand
,
Marian Verhelst
,
Wim Dehaene
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023


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