Georges G. E. Gielen

According to our database1, Georges G. E. Gielen authored at least 300 papers between 1990 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Awards

IEEE Fellow

IEEE Fellow 2002, "For contributions to computer-aided design and design automation of analog and mixed-signal integrated circuits and systems.".

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

Homepages:

On csauthors.net:

Bibliography

2020
A 16.1-bit Resolution 0.064-mm<sup>2</sup> Compact Highly Digital Closed-Loop Single-VCO-Based 1-1 Sturdy-MASH Resistance-to-Digital Converter With High Robustness in 180-nm CMOS.
IEEE J. Solid State Circuits, 2020

Pinhole Latent Defect Modeling and Simulation for Defect-Oriented Analog/Mixed-Signal Testing.
Proceedings of the 38th IEEE VLSI Test Symposium, 2020

Avoiding Mixed-Signal Field Returns by Outlier Detection of Hard-to-Detect Defects based on Multivariate Statistics.
Proceedings of the IEEE European Test Symposium, 2020

Latent Defect Screening with Visually-Enhanced Dynamic Part Average Testing.
Proceedings of the IEEE European Test Symposium, 2020

2019
Understanding the Impact of Time-Dependent Random Variability on Analog ICs: From Single Transistor Measurements to Circuit Simulations.
IEEE Trans. Very Large Scale Integr. Syst., 2019

Performance Limitation Analysis of Highly-Digital Time-Based Closed-Loop Sensor-to-Digital Converter Architectures.
IEEE Trans. Circuits Syst. II Express Briefs, 2019

An 85-MHz-BW ASAR-Assisted CT 4-0 MASH $\Delta\Sigma$ Modulator With Background Half-Range Dithering-Based DAC Calibration in 28-nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

A Robust BBPLL-Based 0.18- $\mu$ m CMOS Resistive Sensor Interface With High Drift Resilience Over a -40 °C-175 °C Temperature Range.
IEEE J. Solid State Circuits, 2019

Architectural Analysis of a Novel Closed-Loop VCO-Based 1-1 Sturdy MASH Sensor-to-Digital Converter.
Proceedings of the 16th International Conference on Synthesis, 2019

From Open-Loop to Closed-Loop Single-VCO-Based Sensor-to-Digital Converter Architectures: theoretical analysis and comparison.
Proceedings of the IEEE 8th International Workshop on Advances in Sensors and Interfaces, 2019

The fantastic voyage towards ultra-miniaturized sensing circuits.
Proceedings of the IEEE 8th International Workshop on Advances in Sensors and Interfaces, 2019

Applying Vstress and defect activation coverage to produce zero-defect mixed-signal automotive ICs.
Proceedings of the IEEE International Test Conference, 2019

Review of Methodologies for Pre- and Post-Silicon Analog Verification in Mixed-Signal SOCs.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

A 16.1-b ENOB 0.064mm<sup>2</sup> Compact Highly-Digital Closed-Loop Single-VCO-based 1-1 SMASH Resistance-to-Digital Converter in 180nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019

2018
A 0.18-µm CMOS Image Sensor With Phase-Delay-Counting and Oversampling Dual-Slope Integrating Column ADCs Achieving 1e<sup>-</sup><sub>rms</sub> Noise at 3.8-µs Conversion Time.
IEEE J. Solid State Circuits, 2018

An Automated Low-Cost Analog and Mixed-Signal DfT Method Using Testing Diodes.
IEEE Des. Test, 2018

ADAGE: Automatic DfT-Assisted Generation of Test Stimuli for Mixed- Signal Integrated Circuits.
IEEE Des. Test, 2018

Generalized mode solver for plasmonic transmission lines embedded in layered media based on the Method of Moments.
Comput. Phys. Commun., 2018

Controlled-Oscillator Optimization for Highly-Digital CMOS Time-Based Sensor-to-Digital Converter Architectures.
Proceedings of the 15th International Conference on Synthesis, 2018

Methodology Towards Sub-ppm Testing of Analog and Mixed-Signal ICs for Cyber-Physical Systems.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Improving the robustness and drift resilience of CMOS BBPLL-based time-based sensor interfaces.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

A Single-Temperature-Calibration 0.18-µm CMOS Time-Based Resistive Sensor Interface with Low Drift over a -40°C to 175°C Temperature Range.
Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018

An 85MHz-BW 68.5dB-SNDR ASAR-assisted CT 4-0 MASH ΔΣ modulator with half-range dithering-based DAC calibration in 28nm CMOS.
Proceedings of the 2018 IEEE Custom Integrated Circuits Conference, 2018

2017
A 0.6-V, 0.015-mm<sup>2</sup>, Time-Based ECG Readout for Ambulatory Applications in 40-nm CMOS.
IEEE J. Solid State Circuits, 2017

Analysis and modeling of drift-resilient time-based integrated resistive sensor interfaces.
Proceedings of the 7th IEEE International Workshop on Advances in Sensors and Interfaces, 2017

Drift mitigation in integrated sensor interfaces.
Proceedings of the 7th IEEE International Workshop on Advances in Sensors and Interfaces, 2017

Non-intrusive detection of defects in mixed-signal integrated circuits using light activation.
Proceedings of the IEEE International Test Conference, 2017

Automatic testing of analog ICs for latent defects using topology modification.
Proceedings of the 22nd IEEE European Test Symposium, 2017

A very low cost and highly parallel DfT method for analog and mixed-signal circuits.
Proceedings of the 22nd IEEE European Test Symposium, 2017

A power-efficient reconfigurable two-step VCO-based ADC for software-defined radio.
Proceedings of the 12th IEEE International Conference on ASIC, 2017

2016
Time-Based Sensor Interface Circuits in CMOS and Carbon Nanotube Technologies.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016

Automatic generation of test infrastructures for analog integrated circuits by controllability and observability co-optimization.
Integr., 2016

Effective DC fault models and testing approach for open defects in analog circuits.
Proceedings of the 2016 IEEE International Test Conference, 2016

Analog fault coverage improvement using final-test dynamic part average testing.
Proceedings of the 2016 IEEE International Test Conference, 2016

Automatic test signal generation for mixed-signal integrated circuits using circuit partitioning and interval analysis.
Proceedings of the 2016 IEEE International Test Conference, 2016

28.5 A 0.6V 0.015mm2 time-based biomedical readout for ambulatory applications in 40nm CMOS.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

A column-and-row-parallel CMOS image sensor with thermal and 1/f noise suppression techniques.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016

A surrogate model assisted evolutionary algorithm for computationally expensive design optimization problems with discrete variables.
Proceedings of the IEEE Congress on Evolutionary Computation, 2016

2015
A 40-MHz Bandwidth 0-2 MASH VCO-Based Delta-Sigma ADC With 35-fJ/Step FoM.
IEEE Trans. Circuits Syst. II Express Briefs, 2015

Development of an Ultralow-Power Injection-Locked PSK Receiver Architecture.
IEEE Trans. Circuits Syst. II Express Briefs, 2015

A 42 fJ/Step-FoM Two-Step VCO-Based Delta-Sigma ADC in 40 nm CMOS.
IEEE J. Solid State Circuits, 2015

Automated testing of mixed-signal integrated circuits by topology modification.
Proceedings of the 33rd IEEE VLSI Test Symposium, 2015

Design of low-power sensor interfaces in the IoT era.
Proceedings of the 6th International Workshop on Advances in Sensors and Interfaces, 2015

Time-based sensor interface circuits in carbon nanotube technology.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

A presence-based control strategy solution for HVAC systems.
Proceedings of the IEEE International Conference on Consumer Electronics, 2015

Automatic generation of autonomous built-in observability structures for analog circuits.
Proceedings of the 20th IEEE European Test Symposium, 2015

A lowpass/bandpass reconfigurable continuous-time ΔΣ ADC for software-defined radio.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

2014
Automated Design of Analog and High-frequency Circuits - A Computational Intelligence Approach
Studies in Computational Intelligence 501, Springer, ISBN: 978-3-642-39161-3, 2014

A Gaussian Process Surrogate Model Assisted Evolutionary Algorithm for Medium Scale Expensive Optimization Problems.
IEEE Trans. Evol. Comput., 2014

A 132-dB Dynamic-Range Global-Shutter Stacked Architecture for High-Performance Imagers.
IEEE Trans. Circuits Syst. II Express Briefs, 2014

Transient Behavior and Phase Noise Performance of Pulsed-Harmonic Oscillators.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014

GASPAD: A General and Efficient mm-Wave Integrated Circuit Synthesis Method Based on Surrogate Model Assisted Evolutionary Algorithm.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Sparse ε-tube support vector regression by active learning.
Soft Comput., 2014

Scalable Bang-Bang Phase-Locked-Loop-based integrated sensor interfaces.
Microelectron. J., 2014

Sensor-to-Digital Interface Built Entirely With Carbon Nanotube FETs.
IEEE J. Solid State Circuits, 2014

An Implantable 455-Active-Electrode 52-Channel CMOS Neural Probe.
IEEE J. Solid State Circuits, 2014

Design and test of analog circuits towards sub-ppm level.
Proceedings of the 2014 International Test Conference, 2014

Design of a frequency reference based on a PVT-independent transmission line delay.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Automatic generation of electro-thermal models with TRAPPIST.
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

Design and implementation of a multi-standard event-driven energy management system for smart buildings.
Proceedings of the IEEE 3rd Global Conference on Consumer Electronics, 2014

Optimization of analog fault coverage by exploiting defect-specific masking.
Proceedings of the 19th IEEE European Test Symposium, 2014

A 40MHz-BW 35fJ/step-FoM nonlinearity-cancelling two-step ADC with dual-input VCO-based quantizer.
Proceedings of the ESSCIRC 2014, 2014

Network on Chip optimization based on surrogate model assisted evolutionary algorithms.
Proceedings of the IEEE Congress on Evolutionary Computation, 2014

Behavioral study of the surrogate model-aware evolutionary search framework.
Proceedings of the IEEE Congress on Evolutionary Computation, 2014

"All Programmable SOC FPGA for networking and computing in big data infrastructure".
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013
Miniaturization of UWB Antennas and its Influence on Antenna-Transceiver Performance in Impulse-UWB Communication.
Wirel. Pers. Commun., 2013

An Efficient Evolutionary Algorithm for Chance-Constrained Bi-Objective Stochastic Optimization.
IEEE Trans. Evol. Comput., 2013

Performance Analysis of Energy-Efficient BBPLL-Based Sensor-to-Digital Converters.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013

Calibration of DAC Mismatch Errors in ΣΔ ADCs Based on a Sine-Wave Measurement.
IEEE Trans. Circuits Syst. II Express Briefs, 2013

Mixed-signal template-based reduction scheme for stimulus artifact removal in electrical stimulation.
Medical Biol. Eng. Comput., 2013

Supply-Noise-Resilient Design of a BBPLL-Based Force-Balanced Wheatstone Bridge Interface in 130-nm CMOS.
IEEE J. Solid State Circuits, 2013

Black-Box Modelling of AC-DC Rectifiers for RFID Applications Using Support Vector Regression Machines.
Proceedings of the 15th International Conference on Computer Modelling and Simulation, 2013

Timing-based integrated sensor interfaces: Hype or promise?
Proceedings of the 5th IEEE International Workshop on Advances in Sensors and Interfaces, 2013

Experimental demonstration of a fully digital capacitive sensor interface built entirely using carbon-nanotube FETs.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

Impact of transistor aging on RF low noise amplifier performance of 28nm technology: Reliability assessment.
Proceedings of the 20th IEEE International Conference on Electronics, 2013


A low-power and low-voltage BBPLL-based sensor interface in 130nm CMOS for wireless sensor networks.
Proceedings of the Design, Automation and Test in Europe, 2013

Extracting analytical nonlinear models from analog circuits by recursive vector fitting of transfer function trajectories.
Proceedings of the Design, Automation and Test in Europe, 2013

Stochastic degradation modeling and simulation for analog integrated circuits in nanometer CMOS.
Proceedings of the Design, Automation and Test in Europe, 2013

Sacha: the Stanford carbon nanotube controlled handshaking robot.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

2012
Characterization of Analog Circuits Using Transfer Function Trajectories.
IEEE Trans. Circuits Syst. I Regul. Pap., 2012

An Efficient High-Frequency Linear RF Amplifier Synthesis Method Based on Evolutionary Computation and Machine Learning Techniques.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

A Multichannel Integrated Circuit for Electrical Recording of Neural Activity, With Independent Channel Programmability.
IEEE Trans. Biomed. Circuits Syst., 2012

Degradation-Resilient Design of a Self-Healing xDSL Line Driver in 90 nm CMOS.
IEEE J. Solid State Circuits, 2012

Sparse multikernel support vector regression machines trained by active learning.
Expert Syst. Appl., 2012

Recurrent sparse support vector regression machines trained by active learning in the time-domain.
Expert Syst. Appl., 2012

Offset measurement method for accurate characterization of BTI-induced degradation in opamps.
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

A 127 μW exact timing reference for Wireless Sensor Networks based on injection locking.
Proceedings of the 38th European Solid-State Circuit conference, 2012

Towards a noise prediction model for in vivo neural recording.
Proceedings of the Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2012

Impact of TSV area on the dynamic range and frame rate performance of 3D-integrated image sensors.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Hierarchical analog circuit reliability analysis using multivariate nonlinear regression and active learning sample selection.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

A fast analog circuit yield estimation method for medium and high dimensional problems.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Advances in variation-aware modeling, verification, and testing of analog ICs.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Design of an intrinsically-linear double-VCO-based ADC with 2<sup>nd</sup>-order noise shaping.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Efficient multi-objective synthesis for microwave components based on computational intelligence techniques.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

Designing reliable analog circuits in an unreliable world.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

Self-adaptive lower confidence bound: A new general and effective prescreening method for Gaussian Process surrogate model assisted evolutionary algorithms.
Proceedings of the IEEE Congress on Evolutionary Computation, 2012

2011
Trustworthy Genetic Programming-Based Synthesis of Analog Circuit Topologies Using Hierarchical Domain-Specific Building Blocks.
IEEE Trans. Evol. Comput., 2011

A Rigorous Approach to the Robust Design of Continuous-Time Sigma-Delta Modulators.
IEEE Trans. Circuits Syst. I Regul. Pap., 2011

A Volterra Series Nonlinear Model of the Sampling Distortion in Flash ADCs Due to Substrate Noise Coupling.
IEEE Trans. Circuits Syst. II Express Briefs, 2011

Synthesis of Integrated Passive Components for High-Frequency RF ICs Based on Evolutionary Computation and Machine Learning Techniques.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Efficient and Accurate Statistical Analog Yield Optimization and Variation-Aware Circuit Sizing Based on Computational Intelligence Techniques.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Computer-Aided Analog Circuit Design for Reliability in Nanometer CMOS.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2011

A 16-channel low-noise programmable system for the recording of neural signals.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

A novel operating-point driven method for the sizing of analog IC.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Circuits and systems engineering education through interdisciplinary team-based design projects.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Impact analysis of stochastic transistor aging on current-steering DACs in 32nm CMOS.
Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011

Efficient analytical macromodeling of large analog circuits by Transfer Function Trajectories.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

A failure-resilient xDSL line driver with on-chip degradation monitor.
Proceedings of the 37th European Solid-State Circuits Conference, 2011

Transistor aging-induced degradation of analog circuits: Impact analysis and design guidelines.
Proceedings of the 37th European Solid-State Circuits Conference, 2011

A fully-digital, 0.3V, 270 nW capacitive sensor interface without external references.
Proceedings of the 37th European Solid-State Circuits Conference, 2011

Stochastic circuit reliability analysis.
Proceedings of the Design, Automation and Test in Europe, 2011

Systematic design of a programmable low-noise CMOS neural interface for cell activity recording.
Proceedings of the Design, Automation and Test in Europe, 2011

Global optimization of integrated transformers for high frequency microwave circuits using a Gaussian process based surrogate model.
Proceedings of the Design, Automation and Test in Europe, 2011

Analog circuit reliability in sub-32 nanometer CMOS: Analysis and mitigation.
Proceedings of the Design, Automation and Test in Europe, 2011

A 40MHz 12bit 84.2dB-SFDR continuous-time delta-sigma modulator in 90nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011

A 0.6V to 1.6V, 46μW voltage and temperature independent 48 MHz pulsed LC oscillator for RFID tags.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011

2010
The Nyquist Criterion: A Useful Tool for the Robust Design of Continuous-Time SigmaDelta Modulators.
IEEE Trans. Circuits Syst. II Express Briefs, 2010

Efficient Variability-Aware NBTI and Hot Carrier Circuit Reliability Analysis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Far-Field On-Chip Antennas Monolithically Integrated in a Wireless-Powered 5.8-GHz Downlink/UWB Uplink RFID Tag in 0.18-μm Standard CMOS.
IEEE J. Solid State Circuits, 2010

A Reconfigurable, 130 nm CMOS 108 pJ/pulse, Fully Integrated IR-UWB Receiver for Communication and Precise Ranging.
IEEE J. Solid State Circuits, 2010

Energy Normalized Correlation for Signal Acquisition in Power-Control-Absent UWB Networks.
IEEE Commun. Lett., 2010

Efficient simulation model for DAC dynamic properties.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

A 0.5 V-1.4 V supply-independent frequency-based analog-to-digital converter with fast start-up time for wireless sensor networks.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Design automation towards reliable analog integrated circuits.
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

Variability-aware reliability simulation of mixed-signal ICs with quasi-linear complexity.
Proceedings of the Design, Automation and Test in Europe, 2010

An accurate and efficient yield optimization method for analog circuits based on computing budget allocation and memetic search technique.
Proceedings of the Design, Automation and Test in Europe, 2010

An enhanced MOEA/D-DE and its application to multiobjective analog cell sizing.
Proceedings of the IEEE Congress on Evolutionary Computation, 2010

2009
A 3-tier UWB-based indoor localization system for ultra-low-power sensor networks.
IEEE Trans. Wirel. Commun., 2009

A memetic approach to the automatic design of high-performance analog integrated circuits.
ACM Trans. Design Autom. Electr. Syst., 2009

Variation-Aware Structural Synthesis of Analog Circuits via Hierarchical Building Blocks and Structural Homotopy.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

Globally Reliable Variation-Aware Sizing of Analog Integrated Circuits via Response Surfaces and Structural Homotopy.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

Template-Free Symbolic Performance Modeling of Analog Circuits via Canonical-Form Functions and Genetic Programming.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

A 70 pJ/Pulse Analog Front-End in 130 nm CMOS for UWB Impulse Radio Receivers.
IEEE J. Solid State Circuits, 2009

ANTIGONE: Top-down creation of analog-to-digital converter architectures.
Integr., 2009

A reconfigurable, 0.13µm CMOS 110pJ/pulse, fully integrated IR-UWB receiver for communication and sub-cm ranging.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

A remote-powered RFID tag with 10Mb/s UWB uplink and -18.5dBm sensitivity UHF downlink in 0.18µm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

Prediction of Non-uniform Sampling Distortion Due to Substrate Noise Coupling in Regenerative Comparators.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

A methodology for measuring transistor ageing effects towards accurate reliability simulation.
Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 2009

Less expensive and high quality stopping criteria for MC-based analog IC yield optimization.
Proceedings of the 16th IEEE International Conference on Electronics, 2009

Optimizing current conveyors by evolutionary algorithms including differential evolution.
Proceedings of the 16th IEEE International Conference on Electronics, 2009

A 0.4-1.4V 24MHz fully integrated 33µW, 104ppm/V supply-independent oscillator for RFIDs.
Proceedings of the 35th European Solid-State Circuits Conference, 2009

RFID, where are they?
Proceedings of the 35th European Solid-State Circuits Conference, 2009

Design tools and circuit solutions for degradation-resilient analog circuits in nanometer CMOS.
Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2009

Massively multi-topology sizing of analog integrated circuits.
Proceedings of the Design, Automation and Test in Europe, 2009

Efficient reliability simulation of analog ICs including variability and time-varying stress.
Proceedings of the Design, Automation and Test in Europe, 2009

A design methodology for fully reconfigurable Delta-Sigma data converters.
Proceedings of the Design, Automation and Test in Europe, 2009

Health-care electronics The market, the challenges, the progress.
Proceedings of the Design, Automation and Test in Europe, 2009

Guess, solder, measure, repeat: how do I get my mixed-signal chip right?
Proceedings of the 46th Design Automation Conference, 2009

Fuzzy selection based differential evolution algorithm for analog cell sizing capturing imprecise human intentions.
Proceedings of the IEEE Congress on Evolutionary Computation, 2009

2008
A Design Approach for Power-Optimized Fully Reconfigurable Delta Sigma A/D Converter for 4G Radios.
IEEE Trans. Circuits Syst. II Express Briefs, 2008

An analytical model for hot carrier degradation in nanoscale CMOS suitable for the simulation of degradation in analog IC applications.
Microelectron. Reliab., 2008

Classification of analog synthesis tools based on their architecture selection mechanisms.
Integr., 2008

Analysis of quantization effects on high-order function neural networks.
Appl. Intell., 2008

A low-power mixing DAC IR-UWB-receiver.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

ISCLEs: Importance Sampled Circuit Learning Ensembles for Trustworthy Analog Circuit Topology Synthesis.
Proceedings of the Evolvable Systems: From Biology to Hardware, 2008

Automated extraction of expert knowledge in analog topology selection and sizing.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

Importance sampled circuit learning ensembles for robust analog IC design.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

A 46pJ/pulse analog front-end in 130nm CMOS for UWB impulse radio receivers.
Proceedings of the ESSCIRC 2008, 2008

Emerging Yield and Reliability Challenges in Nanometer CMOS Technologies.
Proceedings of the Design, Automation and Test in Europe, 2008

From Transistor to PLL - Analogue Design and EDA Methods.
Proceedings of the Design, Automation and Test in Europe, 2008

2007
The Analysis and Improvement of a Current-Steering DAC's Dynamic SFDR - II: The Output-Dependent Delay Differences.
IEEE Trans. Circuits Syst. I Regul. Pap., 2007

Guest Editorial [intro. to the special issue on the 2006 IEEE/ACM Design, Automation and Test in Europe Conference].
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Hierarchical Modeling, Optimization, and Synthesis for System-Level Analog and RF Designs.
Proc. IEEE, 2007

A 14-bit 200-MHz Current-Steering DAC With Switching-Sequence Post-Adjustment Calibration.
IEEE J. Solid State Circuits, 2007

Scalable Gate-Level Models for Power and Timing Analysis.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Effect of Mismatch on Substrate Noise Coupling on Flash A/D Converters.
Proceedings of the 14th IEEE International Conference on Electronics, 2007

Optimal Design Methodology for High-Order Continuous-Time Wideband Delta-Sigma Converters.
Proceedings of the 14th IEEE International Conference on Electronics, 2007

Future trends for wireless communication frontends in nanometer CMOS.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

Analyzing the performance degradation of flash A/D converters due to substrate noise coupling.
Proceedings of the 18th European Conference on Circuit Theory and Design, 2007

Automated synthesis of complex analog circuits.
Proceedings of the 18th European Conference on Circuit Theory and Design, 2007

An efficient methodology for hierarchical synthesis of mixed-signal systems with fully integrated building block topology selection.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Simultaneous Multi-Topology Multi-Objective Sizing Across Thousands of Analog Circuit Topologies.
Proceedings of the 44th Design Automation Conference, 2007

Design tool solutions for mixed-signal/RF circuit design in CMOS nanometer technologies.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006
SWAN: high-level simulation methodology for digital substrate noise generation.
IEEE Trans. Very Large Scale Integr. Syst., 2006

The analysis and improvement of a current-steering DACs dynamic SFDR-I: the cell-dependent delay differences.
IEEE Trans. Circuits Syst. I Regul. Pap., 2006

Evolution of substrate noise generation mechanisms with CMOS technology scaling.
IEEE Trans. Circuits Syst. I Regul. Pap., 2006

Analyzing continuous-time Delta-Sigma-Modulators with generic behavioral models.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Clock-skew-optimization methodology for substrate-noise reduction with supply-current folding.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

A behavioral model of sampled-data systems in the phase-frequency transfer domain for architectural exploration of transceivers.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Assessment of parameter extraction methods for integrated inductor design and model validation.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A Continuous-Time Delta-Sigma Modulator for 802.11a/b/g WLAN Implemented with a Hierarchical Bottom-up Optimization Methodology.
Proceedings of the 13th IEEE International Conference on Electronics, 2006

Automation in mixed-signal design: challenges and solutions in the wake of the nano era.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

Canonical form functions as a simple means for genetic programming to evolve human-interpretable functions.
Proceedings of the Genetic and Evolutionary Computation Conference, 2006

Generic Behavioral Modeling of Analog and Mixed-Signal Systems.
Proceedings of the Forum on specification and Design Languages, 2006

Double-strength CAFFEINE: fast template-free symbolic modeling of analog circuits via implicit canonical form functions and explicit introns.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Top-down heterogeneous synthesis of analog and mixed-signal systems.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Hierarchical bottom--up analog optimization methodology validated by a delta-sigma A/D converter design for the 802.11a/b/g standard.
Proceedings of the 43rd Design Automation Conference, 2006

2005
An Efficient, Fully Parasitic-Aware Power Amplifier Design Optimization Tool.
IEEE Trans. Circuits Syst. I Regul. Pap., 2005

Digital ground bounce reduction by supply current shaping and clock frequency Modulation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

A CAD Platform for Sensor Interfaces in Low-Power Applications.
Proceedings of the Integrated Circuit and System Design, 2005

IBMG: interpretable behavioral model generator for nonlinear analog circuits via canonical form functions and genetic programming.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Analysis of simulation-driven numerical performance modeling techniques for application to analog circuit optimization.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Behavioral modeling and simulation of weakly nonlinear sampled-data systems.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Systematic top-down design of A/D converters.
Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005

A design automation tool for low-power signal filters for use in sensor interfaces.
Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005

Analysis of coil parameter extraction methods for on-chip inductor design.
Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005

CAFFEINE: Template-Free Symbolic Model Generation of Analog Circuits via Canonical Form Functions and Genetic Programming.
Proceedings of the 2005 Design, 2005

Time-Domain Simulation of Sampled Weakly Nonlinear Systems Using Analytical Integration and Orthogonal Polynomial Series.
Proceedings of the 2005 Design, 2005

Analog and Digital Circuit Design in 65 nm CMOS: End of the Road?
Proceedings of the 2005 Design, 2005

Efficient Multiobjective Synthesis of Analog Circuits using Hierarchical Pareto-Optimal Performance Hypersurfaces.
Proceedings of the 2005 Design, 2005

Performance space modeling for hierarchical synthesis of analog integrated circuits.
Proceedings of the 42nd Design Automation Conference, 2005

Efficient symbolic sensitivity analysis of analog circuits using element-coefficient diagrams.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
Efficient analysis of slow-varying oscillator dynamics.
IEEE Trans. Circuits Syst. I Regul. Pap., 2004

A gradient-error and edge-effect tolerant switching scheme for a high-accuracy DAC.
IEEE Trans. Circuits Syst. I Regul. Pap., 2004

Systematic design exploration of delta-sigma ADCs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2004

An analytical integration method for the simulation of continuous-time /spl Delta//spl Sigma/ modulators.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

A Bayesian Classifier by Using the Adaptive Construct Algorithm of the RBF Networks.
Proceedings of the Advances in Neural Networks, 2004

Backpropagation Analysis of the Limited Precision on High-Order Function Neural Networks.
Proceedings of the Advances in Neural Networks, 2004

Knowledge- and optimization-based design of RF power amplifiers.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Modelling of the impact of the current source output impedance on the SFDR of current-steering CMOS D/A converters.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Fast, Layout-Inclusive Analog Circuit Synthesis using Pre-Compiled Parasitic-Aware Symbolic Performance Models.
Proceedings of the 2004 Design, 2004

A Phase-Frequency Transfer Description of Analog and Mixed-Signal Front-End Architectures for System-Level Design.
Proceedings of the 2004 Design, 2004

Performance Modeling of Analog Integrated Circuits Using Least-Squares Support Vector Machines.
Proceedings of the 2004 Design, 2004

Digital Ground Bounce Reduction by Phase Modulation of the Clock.
Proceedings of the 2004 Design, 2004

High-level simulation of substrate noise in high-ohmic substrates with interconnect and supply effects.
Proceedings of the 41th Design Automation Conference, 2004

Impact of technology scaling on substrate noise generation mechanisms [mixed signal ICs].
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004

High-level modeling of continuous-time Delta-Sigma A/D-converters using formal models.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003
PeopleMover: an example of interdisciplinary project-based education in electrical engineering.
IEEE Trans. Educ., 2003

Behavioral modeling of (coupled) harmonic oscillators.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

WATSON: design space boundary exploration and model generation for analog and RFIC design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

Guest editorial.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

A high-level simulation and synthesis environment for /spl Delta//spl Sigma/ modulators.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

Simulation-based generation of posynomial performance models for the sizing of analog integrated circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

The Effects of Quantization on Multi-Layer Feedforward Neural Networks.
Int. J. Pattern Recognit. Artif. Intell., 2003

Fast Learning Algorithms for Feedforward Neural Networks.
Appl. Intell., 2003

Analysis of the dynamic SFDR property of high-accuracy current-steering D/A converters.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

A Generalized Method for Computing Oscillator Phase Noise Spectra.
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

Figure of Merit Based Selection of A/D Converters.
Proceedings of the 2003 Design, 2003

Time-Varying, Frequency-Domain Modeling and Analysis of Phase-Locked Loops with Sampling Phase-Frequency Detectors.
Proceedings of the 2003 Design, 2003

HOLMES: Capturing the Yield-Optimized Design Space Boundaries of Analog and RF Integrated Circuits.
Proceedings of the 2003 Design, 2003

A Model of Computation for Continuous-Time ?-? Modulators.
Proceedings of the 2003 Design, 2003

Generalized Posynomial Performance Modeling.
Proceedings of the 2003 Design, 2003

Behavioral Modeling and Simulation of a Mixed Analog/Digital Automatic Gain Control Loop in a 5 GHz WLAN Receiver.
Proceedings of the 2003 Design, 2003

Architectural selection of A/D converters.
Proceedings of the 40th Design Automation Conference, 2003

2002
Power estimation methods for analog circuits for architectural exploration of integrated systems.
IEEE Trans. Very Large Scale Integr. Syst., 2002

Symbolic modeling of periodically time-varying systems usingharmonic transfer matrices.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

CYCLONE: automated design and layout of RF LC-oscillators.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

A layout synthesis methodology for array-type analog blocks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

Circuit simplification for the symbolic analysis of analogintegrated circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

A fast learning algorithm for time-delay neural networks.
Inf. Sci., 2002

Editorial.
Integr., 2002

Braille to print translations for Chinese.
Inf. Softw. Technol., 2002

Efficient time-domain simulation of continuous-time Delta-Sigma A/D converters using analytical integration.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Regression criteria and their application in different modeling cases.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

On the difference between two widely publicized methods for analyzing oscillator phase behavior.
Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

A behavioral simulation tool for continuous-time delta sigma modulators.
Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

Systematic Design of a 200 Ms/S 8-bit Interpolating A/D Converter.
Proceedings of the 2002 Design, 2002

Constructing Symbolic Models for the Input/Output Behavior of Periodically Time-Varying Systems Using Harmonic Transfer Matrices.
Proceedings of the 2002 Design, 2002

DAISY-CT: A High-Level Simulation Tool for Continuous-Time Delta Sigma Modulators.
Proceedings of the 2002 Design, 2002

A Fitting Approach to Generate Symbolic Expressions for Linear and Nonlinear Analog Circuit Performance Characteristics.
Proceedings of the 2002 Design, 2002

Systematic design of a 200 MS/s 8-bit interpolating/averaging A/D converter.
Proceedings of the 39th Design Automation Conference, 2002

An efficient optimization--based technique to generate posynomial performance models for analog integrated circuits.
Proceedings of the 39th Design Automation Conference, 2002

Optimal design of delta-sigma ADCs by design space exploration.
Proceedings of the 39th Design Automation Conference, 2002

Clock tree optimization in synchronous CMOS digital circuits for substrate noise reduction using folding of supply current transients.
Proceedings of the 39th Design Automation Conference, 2002

2001
AMGIE-A synthesis environment for CMOS analog integrated circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

A Layout-Aware Synthesis Methodology for RF Circuits.
Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

Embedded Tutorial: CAD Solutions and Outstanding Challenges for Mixed-Signal and RF IC Design.
Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

Simulation-Based Automatic Generation of Signomial and Posynomial Performance Models for Analog Integrated Circuit Sizing.
Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

Efficient time-domain simulation of telecom frontends using a complex damped exponential signal model.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

Design challenges and emerging EDA solutions in mixed-signal IC design.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

High-level simulation of substrate noise generation from large digital circuits with multiple supplies.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

Efficient DDD-based Symbolic Analysis of Large Linear Analog Circuits.
Proceedings of the 38th Design Automation Conference, 2001

Panel: When Will the Analog Design Flow Catch Up with Digital Methodology?
Proceedings of the 38th Design Automation Conference, 2001

2000
Efficient analysis of the stability of sigma-delta modulators using wavelets.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

ACTIF: A High-Level Power Estimation Tool for Analog Continuous-Time-Filters.
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

DAISY: A Simulation-Based High-Level Synthesis Tool for Delta-Sigma Modulators.
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

Optimal RF design using smart evolutionary algorithms.
Proceedings of the 37th Conference on Design Automation, 2000

CYCLONE: automated design and layout of RF LC-oscillators.
Proceedings of the 37th Conference on Design Automation, 2000

Systematic design of a 14-bit 150-MS/s CMOS current-steering D/A converter.
Proceedings of the 37th Conference on Design Automation, 2000

Survival strategies for mixed-signal systems-on-chip (panel session).
Proceedings of the 37th Conference on Design Automation, 2000

Modeling and Simulation of a Sigma-Delta Digital to Analog Converter Using VHDL-AMS.
Proceedings of the 2000 IEEE/ACM International Workshop on Behavioral Modeling and Simulation, 2000

High-Level Design Case of a Switched-Capacitor Low-Pass Filter Using Verilog-A.
Proceedings of the 2000 IEEE/ACM International Workshop on Behavioral Modeling and Simulation, 2000

1999
Methodology for analog technology porting including performance tuning.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

A Power Estimation Model for High-Speed CMOS A/D Converters.
Proceedings of the 1999 Design, 1999

Circuit Complexity Reduction for Symbolic Analysis of Analog Integrated Circuits.
Proceedings of the 36th Conference on Design Automation, 1999

1998
Probabilistic fault detection and the selection of measurements for analog integrated circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

High-Level Power Minimization of Analog Sensor Interface Architectures.
Integr. Comput. Aided Eng., 1998

An efficient DC root solving algorithm with guaranteed convergence for analog integrated CMOS circuits.
Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

Efficient analog circuit synthesis with simultaneous yield and robustness optimization.
Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

Hierarchical Top-Down Design of Analog Sensor Interfaces: From System-Level Specifications Down to Silicon.
Proceedings of the 1998 Design, 1998

1997
Automated test pattern generation for analog integrated circuits.
Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997

A behavioral signal path modeling methodology for qualitative insight in and efficient sizing of CMOS opamps.
Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

High-level synthesis of analog sensor interface front-ends.
Proceedings of the European Design and Test Conference, 1997

1996
Synthesis Tools for Mixed-Signal ICs: Progress on Frontend and Backend Strategies.
Proceedings of the 33st Conference on Design Automation, 1996

1995
An analogue module generator for mixed analogue/digital asic design.
Int. J. Circuit Theory Appl., 1995

Use of Symbolic Analysis in Analog Circuit Synthesis.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

A high-level design and optimization tool for analog RF receiver front-ends.
Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

A flexible topology selection program as part of an analog synthesis system.
Proceedings of the 1995 European Design and Test Conference, 1995

Direct Performance-Driven Placement of Mismatch-Sensitive Analog Circuits.
Proceedings of the 32st Conference on Design Automation, 1995

1994
A Novel Method for the Fault Detection of Analog Integrated Circuits.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

Symbolic Analysis of Large Analog Integrated Circuits by Approximation During Expression Generation.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

Pleasures, Perils and Pitfalls of Symbolic Analysis.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

Fault detection and input stimulus determination for the testing of analog integrated circuits based on power-supply current monitoring.
Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

A Methodology for Analog Design Automation in Mixed-Signal ASICs.
Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

1993
Modeling of the Power-supply Interactions of CMOS Operational Amplifiers Using Symbolic Computation.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

1991
A Behavioral Representation for Nyquist Rate A/D Converters.
Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

Interactive symbolic distortion analysis of analogue integrated circuits.
Proceedings of the conference on European design automation, 1991

Symbolic analysis for automated design of analog integrated circuits.
The Kluwer international series in engineering and computer science 137, Kluwer, ISBN: 978-0-7923-9161-6, 1991

1990
An intelligent design system for analogue integrated circuits.
Proceedings of the European Design Automation Conference, 1990


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