Pouya Houshmand
Orcid: 0000-0003-2935-8842
According to our database1,
Pouya Houshmand
authored at least 10 papers
between 2020 and 2023.
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Bibliography
2023
IEEE J. Solid State Circuits, 2023
Benchmarking and modeling of analog and digital SRAM in-memory computing architectures.
CoRR, 2023
Stream: A Modeling Framework for Fine-grained Layer Fusion on Multi-core DNN Accelerators.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2023
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023
A 16nm 128kB high-density fully digital In Memory Compute macro with reverse SRAM pre-charge achieving 0.36TOPs/mm<sup>2</sup>, 256kB/mm<sup>2</sup> and 23. 8TOPs/W.
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023
2022
Towards Heterogeneous Multi-core Accelerators Exploiting Fine-grained Scheduling of Layer-Fused Deep Neural Networks.
CoRR, 2022
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
2021
ZigZag: Enlarging Joint Architecture-Mapping Design Space Exploration for DNN Accelerators.
IEEE Trans. Computers, 2021
Hardware-Efficient Residual Neural Network Execution in Line-Buffer Depth-First Processing.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2021
2020
CoRR, 2020