Wilfried Daehn

According to our database1, Wilfried Daehn
  • authored at least 18 papers between 1981 and 1998.
  • has a "Dijkstra number"2 of five.

Timeline

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Bibliography

1998
An Open Simulation and Modeling Environment for Embedded Real-Time Systems.
Proceedings of the Ninth IEEE International Workshop on Rapid System Prototyping (RSP 1998), 1998

A Central Control Engine for an Open and Hybrid Simulation Environment.
Proceedings of the 2nd International Workshop on Distributed Interactive Simulation and Real-Time Applications (DIS-RT '98), 1998

1995
Electrosmog & electromagnetic CAD.
Future Generation Comp. Syst., 1995

Fault modeling of differential ECL.
Proceedings of the Proceedings EURO-DAC'95, 1995

1994
Electrosmog and Electromagnetic CAD (Invited Paper).
Proceedings of the High-Performance Computing and Networking, 1994

Distributed simulation for structural VHDL netlists.
Proceedings of the Proceedings EURO-DAC'94, 1994

1991
Iterative algorithms for computing aliasing probabilities.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1991

Load Balancing in a Hybrid ATPG Environment.
IEEE Trans. Computers, 1991

Fault simulation using small fault samples.
J. Electronic Testing, 1991

1990
Contest: A Fast ATPG Tool for Very Large Combinatorial Circuits.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990

Accelerated test pattern generation by cone-oriented circuit partitioning.
Proceedings of the European Design Automation Conference, 1990

1988
Bounds and analysis of aliasing errors in linear feedback shift registers.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1988

1986
Comparison of Aliasing Errors for Primitive and Non-Primitive Polynomials.
Proceedings of the Proceedings International Test Conference 1986, 1986

A Test Generator IC for Testing Large CMOS-RAMs.
Proceedings of the Proceedings International Test Conference 1986, 1986

A unified treatment of PLA faults by Boolean differences.
Proceedings of the 23rd ACM/IEEE Design Automation Conference. Las Vegas, NV, June, 1986., 1986

1982
Ein 32-Bit-Rechenwerk mit eingebautem Hardware-Selbsttest.
Proceedings of the Fehlertolerierende Rechensysteme, 1982

1981
A Hardware Approach to Self-Testing of Large Programmable Logic Arrays.
IEEE Trans. Computers, 1981

Hardware Test Pattern Generation for Built-In Testing.
Proceedings of the Proceedings International Test Conference 1981, 1981


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