Thomas W. Williams

According to our database, Thomas W. Williams authored at least 65 papers between 1972 and 2008.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2008

Historical Perspective on Scan Compression.

Rohit Kapur, Subhasish Mitra, Thomas W. Williams

IEEE Des. Test Comput., 2008

EDA to the Rescue of the Silicon Roadmap.

Thomas W. Williams

Proceedings of the 38th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2008), 2008

The Future Is Low Power and Test.

Thomas W. Williams

Proceedings of the 13th European Test Symposium, 2008

Evaluation of Entropy Driven Compression Bounds on Industrial Designs.

Srinivasulu Alampally, Jais Abraham, Rubin A. Parekhji, Rohit Kapur, Thomas W. Williams

Proceedings of the 17th IEEE Asian Test Symposium, 2008

Reaching the limits of low power design.

J. S. Hobbs, Thomas W. Williams

Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007

DFT MAX and Power.

Rohit Kapur, T. Finklea, Felix Ng, Anshuman Chandra, Sanjay Ramnath, Peter Wohl, Thomas W. Williams, Ashok Anbalan, Sandeep S. Kulkarni, Tammy Fernandes, Pramod Notiyath, Rajesh Uppuluri

J. Low Power Electron., 2007

Minimizing the Impact of Scan Compression.

Peter Wohl, John A. Waicukauski, Rohit Kapur, Sanjay Ramnath, Emil Gizdarski, Thomas W. Williams, P. Jaini

Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007

Fundamentals of timing information for test: How simple can we get?

Rohit Kapur, Jindrich Zejda, Thomas W. Williams

Proceedings of the 2007 IEEE International Test Conference, 2007

Accurately Determining Bridging Defects from Layout.

Maria Gkatziani, Rohit Kapur, Qing Su, Ben Mathew, Roberto Mattiuzzo, Laura Tarantini, Cy Hay, Salvatore Talluto, Thomas W. Williams

Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), 2007

2005

TTTC recognizes test visionary's lifetime contribution.

Thomas W. Williams

IEEE Des. Test Comput., 2005

Efficient compression of deterministic patterns into multiple PRPG seeds.

Peter Wohl, John A. Waicukauski, Sanjay Patel, Francisco DaSilva, Thomas W. Williams, Rohit Kapur

Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

Design for Testability: The Path to Deep Submicron.

Thomas W. Williams

Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

2004

Changing the Scan Enable during Shift.

Nodari Sitchinava, Samitha Samaranayake, Rohit Kapur, Emil Gizdarski, Frederic Neuveux, Thomas W. Williams

Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004

2003

A Reconfigurable Shared Scan-in Architecture.

Samitha Samaranayake, Emil Gizdarski, Nodari Sitchinava, Frederic Neuveux, Rohit Kapur, Thomas W. Williams

Proceedings of the 21st IEEE VLSI Test Symposium (VTS 2003), 27 April, 2003

Using Logic Models To Predict The Detection Behavior Of Statistical Timing Defects.

Li-C. Wang, Angela Krstic, Leonard Lee, Kwang-Ting Cheng, M. Ray Mercer, Thomas W. Williams, Magdy S. Abadir

Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

Test Pattern Compression Using Prelude Vectors in Fan-Out Scan Chain with Feedback Architecture.

Nahmsuk Oh, Rohit Kapur, Thomas W. Williams, Jim Sproch

Proceedings of the 2003 Design, 2003

2002

Dynamic Scan: Driving Down the Cost of Test.

Samitha Samaranayake, Nodari Sitchinava, Rohit Kapur, Minesh B. Amin, Thomas W. Williams

Computer, 2002

Analysis of Delay Test Effectiveness with a Multiple-Clock Scheme.

Jing-Jia Liou, Li-C. Wang, Kwang-Ting Cheng, Jennifer Dworak, M. Ray Mercer, Rohit Kapur, Thomas W. Williams

Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

Fast seed computation for reseeding shift register in test pattern compression.

Nahmsuk Oh, Rohit Kapur, Thomas W. Williams

Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

Directed-Binary Search in Logic BIST Diagnostics.

Rohit Kapur, Thomas W. Williams, M. Ray Mercer

Proceedings of the 2002 Design, 2002

Enhancing test efficiency for delay fault testing using multiple-clocked schemes.

Jing-Jia Liou, Li-C. Wang, Kwang-Ting Cheng, Jennifer Dworak, M. Ray Mercer, Rohit Kapur, Thomas W. Williams

Proceedings of the 39th Design Automation Conference, 2002

Manufacturing Test of SoCs.

Rohit Kapur, Thomas W. Williams

Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002

2001

Strategies for Low-Cost Test.

Rohit Kapur, R. Chandramouli, Thomas W. Williams

IEEE Des. Test Comput., 2001

Design of compactors for signature-analyzers in built-in self-test.

Peter Wohl, John A. Waicukauski, Thomas W. Williams

Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

A new methodology for improved tester utilization.

Ajay Khoche, Rohit Kapur, David Armstrong, Thomas W. Williams, Mick Tegethoff, Jochen Rivoir

Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

Tester retargetable patterns.

Rohit Kapur, Thomas W. Williams

Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

2000

An industrial view of electronic design automation.

Don MacMillen, Raul Camposano, Dwight D. Hill, Thomas W. Williams

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

The Mutating Metric for Benchmarking Test.

Rohit Kapur, Cy Hay, Thomas W. Williams

IEEE Des. Test Comput., 2000

How Should Fault Coverage Be Defined?

Thomas W. Williams, Stephen K. Sunter

Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000

Design for Testability in Nanometer Technologies; Searching for Quality.

Thomas W. Williams, Rohit Kapur

Proceedings of the 1st International Symposium on Quality of Electronic Design (ISQED 2000), 2000

DFT closure.

Farhad Hayat, Thomas W. Williams, Rohit Kapur, D. Hsu

Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

1999

IEEE-USA and the Issue of Member Choice.

Thomas W. Williams

Computer, 1999

Tough Challenges as Design and Test Go Nanometer - Guest Editors' Introduction.

Rohit Kapur, Thomas W. Williams

Computer, 1999

Testing in Nanometer Technologies.

Thomas W. Williams

Proceedings of the 1999 Design, 1999

1998

The New Frontier for Testing: Nano Meter Technologies.

Thomas W. Williams

Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998

1996

Defect level evaluation in an IC design environment.

José T. de Sousa, Fernando M. Gonçalves, João Paulo Teixeira, Cristoforo Marzocca, Francesco Corsi, Thomas W. Williams

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996

A weighted random pattern test generation system.

Rohit Kapur, Srinivas Patil, Thomas J. Snethen, Thomas W. Williams

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996

I_DDQ Test: Sensitivity Analysis of Scaling.

Thomas W. Williams, Robert H. Dennard, Rohit Kapur, M. Ray Mercer, Wojciech Maly

Proceedings of the Proceedings IEEE International Test Conference 1996, 1996

Using Target Faults To Detect Non-Tartget Defects.

Li-C. Wang, M. Ray Mercer, Thomas W. Williams

Proceedings of the Proceedings IEEE International Test Conference 1996, 1996

A Better ATPG Algorithm and Its Design Principles.

Li-C. Wang, M. Ray Mercer, Thomas W. Williams

Proceedings of the 1996 International Conference on Computer Design (ICCD '96), 1996

Iddq Testing for High Performance CMOS - The Next Ten Years.

Thomas W. Williams, Rohit Kapur, M. Ray Mercer, Robert H. Dennard, Wojciech Maly

Proceedings of the 1996 European Design and Test Conference, 1996

1995

On the decline of testing efficiency as fault coverage approaches 100%.

Li-C. Wang, M. Ray Mercer, Sophia W. Kao, Thomas W. Williams

Proceedings of the 13th IEEE VLSI Test Symposium (VTS'95), April 30, 1995

On Efficiently and Reliably Achieving Low Defective Part Levels.

Li-C. Wang, M. Ray Mercer, Thomas W. Williams

Proceedings of the Proceedings IEEE International Test Conference 1995, 1995

Enhanced testing performance via unbiased test sets.

Li-C. Wang, M. Ray Mercer, Thomas W. Williams

Proceedings of the 1995 European Design and Test Conference, 1995

1994

Limitations in predicting defect level based on stuck-at fault coverage.

Jaehong Park, Mark Naivar, Rohit Kapur, M. Ray Mercer, Thomas W. Williams

Proceedings of the 12th IEEE VLSI Test Symposium (VTS'94), 1994

Design of an Efficient Weighted-Random-Pattern Generation System.

Rohit Kapur, Srinivas Patil, Thomas J. Snethen, Thomas W. Williams

Proceedings of the Proceedings IEEE International Test Conference 1994, 1994

Fault Modeling and Defect Level Projections in Digital ICs.

José T. de Sousa, Fernando M. Gonçalves, João Paulo Teixeira, Thomas W. Williams

Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

1993

Design for Testability: Today and in the Future.

Thomas W. Williams

Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993

1992

The Total Delay Fault Model and Statistical Delay Fault Coverage.

Eun Sei Park, M. Ray Mercer, Thomas W. Williams

IEEE Trans. Computers, 1992

1991

Enhancing Board Functional Self-Test by Concurrent Sampling.

Kenneth D. Wagner, Thomas W. Williams

Proceedings of the Proceedings IEEE International Test Conference 1991, 1991

Delay Testing Quality in Timing-Optimized Designs.

Eun Sei Park, Bill Underwood, Thomas W. Williams, M. Ray Mercer

Proceedings of the Proceedings IEEE International Test Conference 1991, 1991

The Interdependence Between Delay-Optimization of Synthesized Networks and Testing.

Thomas W. Williams, Bill Underwood, M. Ray Mercer

Proceedings of the 28th Design Automation Conference, 1991

1989

A statistical model for delay-fault testing.

Eun Sei Park, M. Ray Mercer, Thomas W. Williams

IEEE Des. Test, 1989

Future Trends in the Testing.

Thomas W. Williams

Proceedings of the Information Processing 89, Proceedings of the IFIP 11th World Computer Congress, San Francisco, USA, August 28, 1989

1988

Design for Testability of Mixed Signal Integrated Circuits.

Kenneth D. Wagner, Thomas W. Williams

Proceedings of the Proceedings International Test Conference 1988, 1988

Statistical Delay Fault Coverage and Defect Level for Delay Faults.

Eun Sei Park, Thomas W. Williams, M. Ray Mercer

Proceedings of the Proceedings International Test Conference 1988, 1988

1986

Design of testable logic circuits.

Thomas W. Williams

Proc. IEEE, 1986

1985

Test Length in a Self-Testing Environment.

Thomas W. Williams

IEEE Des. Test, 1985

1984

VLSI Testing.

Thomas W. Williams

Computer, 1984

1982

Design for Testability - A Survey.

Thomas W. Williams, Kenneth P. Parker

IEEE Trans. Computers, 1982

Analysis of the Switching Behavior of Combinatorial Logic Networks.

Eugen I. Muehldorf, Thomas W. Williams

Proceedings of the Proceedings International Test Conference 1982, 1982

Design for testability.

Thomas W. Williams

Proceedings of the 19th Design Automation Conference, 1982

1979

Testing Logic Networks and Designing for Testability.

Thomas W. Williams, Kenneth P. Parker

Computer, 1979

1977

A logic design structure for LSI testability.

Edward B. Eichelberger, Thomas W. Williams

Proceedings of the 14th Design Automation Conference, 1977

1972

Effect of Record Length on Noise-Induced Error in the Cross Correlation Estimate.

Daniel J. Krause, John W. Steadman, Thomas W. Williams

IEEE Trans. Syst. Man Cybern., 1972