André Ivanov

According to our database, André Ivanov authored at least 143 papers between 1986 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2024

VioNet: A Hierarchical Detailed Routing Wire-Short Violation Predictor Based on a Convolutional Neural Network.

Yuxuan Pan, Zhonghua Zhou, S. Arash Sheikholeslam, André Ivanov

IEEE Des. Test, 2024

2023

MEDUSA: A Multi-Resolution Machine Learning Congestion Estimation Method for 2D and 3D Global Routing.

Zhonghua Zhou, Yuxuan Pan, Guy G. F. Lemieux, André Ivanov

ACM Trans. Design Autom. Electr. Syst., September, 2023

Gerabaldi: A Temporal Simulator for Probabilistic IC Degradation and Failure Processes.

Ian Hill, André Ivanov

Proceedings of the 41st IEEE VLSI Test Symposium, 2023

2022

Routability-driven Global Routing with 3D Congestion Estimation Using a Customized Neural Network.

Yuxuan Pan, Zhonghua Zhou, André Ivanov

Proceedings of the 23rd International Symposium on Quality Electronic Design, 2022

Prediction of Thermally Accelerated Aging Process at 28nm.

Parvez Anwar Chanawala, Ian Hill, S. Arash Sheikholeslam, André Ivanov

Proceedings of the IEEE European Test Symposium, 2022

2021

Are you for Real? Authentication in Dynamic IoT Systems.

Mehdi Karimibiuki, Karthik Pattabiraman, André Ivanov

Proceedings of the 26th IEEE Pacific Rim International Symposium on Dependable Computing, 2021

2019

Supervised-Learning Congestion Predictor For Routability-Driven Global Routing.

Zhonghua Zhou, Sunmeet Chahal, Tsung-Yi Ho, André Ivanov

Proceedings of the International Symposium on VLSI Design, Automation and Test, 2019

2018

DynPolAC: Dynamic Policy-Based Access Control for IoT Systems.

Mehdi Karimibiuki, Ekta Aggarwal, Karthik Pattabiraman, André Ivanov

Proceedings of the 23rd IEEE Pacific Rim International Symposium on Dependable Computing, 2018

MiniCloud: a mini storage and query service for local heterogeneous IoT devices.

Mehdi Karimibiuki, André Ivanov

Proceedings of the 8th International Conference on the Internet of Things, 2018

CORGIDS: A Correlation-based Generic Intrusion Detection System.

Ekta Aggarwal, Mehdi Karimibiuki, Karthik Pattabiraman, André Ivanov

Proceedings of the 2018 Workshop on Cyber-Physical Systems Security and PrivaCy, 2018

2016

An improved test power optimization method by insertion of linear functions.

Lucheng He, Aijiao Cui, Mengyang Li, André Ivanov

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Local congestion and blockage aware routability analysis using adaptive flexible modeling.

André Ivanov, Peter Hallschmid, Zhonghua Zhou

Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

2015

Microfluidics: Design and Test Solutions for Enabling Biochemistry on a Chip.

André Ivanov

IEEE Des. Test, 2015

Cyber-Physplical Systems for Medical Apications.

André Ivanov

IEEE Des. Test, 2015

Advances in 3-D Integrated Circuits, Systems, and CAD Tools.

André Ivanov

IEEE Des. Test, 2015

A Look at Asynchronous Design and Photonic Network-on-a-Chip (PNoC).

André Ivanov

IEEE Des. Test, 2015

A Look at Trojan Attack, Pruning, and Dependability.

André Ivanov

IEEE Des. Test, 2015

Speeding Up Analog Integration and Test for Mixed-Signal SoCs.

André Ivanov

IEEE Des. Test, 2015

A new decompressor with ordered parallel scan design for reduction of test data and test time.

Tingting Yu, Aijiao Cui, Mengyang Li, André Ivanov

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Reducing Post-Silicon Coverage Monitoring Overhead with Emulation and Bayesian Feature Selection.

Ricardo Ochoa Gallardo, Alan J. Hu, André Ivanov, Maryam S. Mirian

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

2014

Design and Testing of Millimeter-Wave/Subterahertz Circuits and Systems.

André Ivanov

IEEE Des. Test, 2014

The Internet of Things.

André Ivanov

IEEE Des. Test, 2014

Revisiting DAC's 50th Anniversary.

André Ivanov

IEEE Des. Test, 2014

T1B: Wireless NoC as interconnection backbone for multicore chips: Promises and challenges.

Partha Pratim Pande, Alireza Nojeh, André Ivanov

Proceedings of the 27th IEEE International System-on-Chip Conference, 2014

T2B: Carbon nanotubes and opportunities for wireless on-chip interconnect.

Alireza Nojeh, Partha Pratim Pande, André Ivanov

Proceedings of the 27th IEEE International System-on-Chip Conference, 2014

A low-power DC-to-27-GHz transimpedance amplifier in 0.13-µm CMOS using inductive-peaking and current-reuse techniques.

Amir Hossein Masnadi Shirazi, Reza Molavi, Peter Sangpil Woo, Ge Yu, Shahriar Mirabbasi, Sudip Shekhar, André Ivanov

Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014

A novel tri-state device implemented with a metal gated QCA.

S. Arash Sheikholeslam, Cristian Grecu, André Ivanov

Proceedings of the IEEE 5th Latin American Symposium on Circuits and Systems, 2014

Performance comparison of two wide-tuning-range 13-GHz CMOS LC-VCOs.

Ge Yu, Shahriar Mirabbasi, André Ivanov

Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

2013

Post-Silicon Code Coverage for Multiprocessor System-on-Chip Designs.

Kyle Balston, Mehdi Karimibiuki, Alan J. Hu, André Ivanov, Steven J. E. Wilton

IEEE Trans. Computers, 2013

2012

Multi-objective voltage island floorplanning using sequence pair representation.

Dipanjan Sengupta, Andreas G. Veneris, Steven J. E. Wilton, André Ivanov

Sustain. Comput. Informatics Syst., 2012

Lazy suspect-set computation: fault diagnosis for deep electrical bugs.

Dipanjan Sengupta, Flavio M. de Paula, Alan J. Hu, Andreas G. Veneris, André Ivanov

Proceedings of the Great Lakes Symposium on VLSI 2012, 2012

2011

Ring oscillators for functional and delay test of latches and flip-flops.

Renato P. Ribas, Yuyang Sun, André Inácio Reis, André Ivanov

Proceedings of the 24th Symposium on Integrated Circuits and Systems Design, 2011

Self-checking test circuits for latches and flip-flops.

Renato P. Ribas, Yuyang Sun, André Inácio Reis, André Ivanov

Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011

Performance and functional test of flip-flops using ring oscillator structure.

Renato P. Ribas, André Inácio Reis, André Ivanov

Proceedings of the 6th IEEE International Design and Test Workshop, 2011

Post-silicon code coverage evaluation with reduced area overhead for functional verification of SoC.

Mehdi Karimibiuki, Kyle Balston, Alan J. Hu, André Ivanov

Proceedings of the 2011 IEEE International High Level Design Validation and Test Workshop, 2011

Sequence pair based voltage island floorplanning.

Dipanjan Sengupta, Andreas G. Veneris, Steven J. E. Wilton, André Ivanov, Res Saleh

Proceedings of the 2011 International Green Computing Conference and Workshops, 2011

2010

Wireless Interconnect and the Potential for Carbon Nanotubes.

Alireza Nojeh, André Ivanov

IEEE Des. Test Comput., 2010

2009

Application modelling and hardware description for network-on-chip benchmarking.

Erno Salminen, Cristian Grecu, Timo D. Hämäläinen, André Ivanov

IET Comput. Digit. Tech., 2009

Modeling and Evaluating Errors Due to Random Clock Shifts in Quantum-Dot Cellular Automata Circuits.

Faizal Karim, Marco Ottavi, Hamidreza Hashempour, Vamsi Vankamamidi, Konrad Walus, André Ivanov, Fabrizio Lombardi

J. Electron. Test., 2009

2008

An FPGA Design Project: Creating a PowerPC Subsystem Plus User Logic.

Rod Blaine Foist, Cristian Grecu, André Ivanov, Robin Turner

IEEE Trans. Educ., 2008

Novel interconnect infrastructures for massive multicore chips - an overview.

Partha Pratim Pande, Amlan Ganguly, Benjamin Belzer, Alireza Nojeh, André Ivanov

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

2007

Design of a Tunable Differential Ring Oscillator With Short Start-Up and Switching Transients.

A. K. M. K. Mollah, Roberto Rosales, Sassan Tabatabaei, James Cicalo, André Ivanov

IEEE Trans. Circuits Syst. I Regul. Pap., 2007

Testing Network-on-Chip Communication Fabrics.

Cristian Grecu, André Ivanov, Resve A. Saleh, Partha Pratim Pande

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Design and implementation of reconfigurable and flexible test access mechanism for system-on-chip.

Zahra Sadat Ebadi, Alireza Nasiri Avanaki, Resve A. Saleh, André Ivanov

Integr., 2007

Test scheduling for built-in self-tested embedded SRAMs with data retention faults.

Qiang Xu, Baosheng Wang, André Ivanov, Fung Yu Young

IET Comput. Digit. Tech., 2007

Towards Open Network-on-Chip Benchmarks.

Cristian Grecu, André Ivanov, Partha Pratim Pande, Axel Jantsch, Erno Salminen, Ümit Y. Ogras, Radu Marculescu

Proceedings of the First International Symposium on Networks-on-Chips, 2007

An FPGA Design Project: Creating a PowerPC Subsystem Plus User Logic.

Rod Blaine Foist, André Ivanov, Robin Turner

Proceedings of the IEEE International Conference on Microelectronic Systems Education, 2007

Essential Fault-Tolerance Metrics for NoC Infrastructures.

Cristian Grecu, Lorena Anghel, Partha Pratim Pande, André Ivanov, Resve A. Saleh

Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007

On the Error Effects of Random Clock Shifts in Quantum-Dot Cellular Automata Circuits.

Marco Ottavi, Hamidreza Hashempour, Vamsi Vankamamidi, Faizal Karim, Konrad Walus, André Ivanov

Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007

A 43 mW single-channel 4GS/s 4-bit flash ADC in 0.18 μm CMOS.

Samad Sheikhaei, Shahriar Mirabbasi, André Ivanov

Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2006

Fast detection of data retention faults and other SRAM cell open defects.

Josh Yang, Baosheng Wang, Yuejian Wu, André Ivanov

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

System-on-Chip: Reuse and Integration.

Resve A. Saleh, Steven J. E. Wilton, Shahriar Mirabbasi, Alan J. Hu, Mark R. Greenstreet, Guy Lemieux, Partha Pratim Pande, Cristian Grecu, André Ivanov

Proc. IEEE, 2006

Session Abstract.

André Ivanov

Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

BIST for Network-on-Chip Interconnect Infrastructures.

Cristian Grecu, Partha Pratim Pande, André Ivanov, Res Saleh

Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

On-line Fault Detection and Location for NoC Interconnects.

Cristian Grecu, André Ivanov, Res Saleh, Egor S. Sogomonyan, Partha Pratim Pande

Proceedings of the 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 2006

Low Power SoC Memory BIST.

Yuejian Wu, André Ivanov

Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006

NoC Interconnect Yield Improvement Using Crosspoint Redundancy.

Cristian Grecu, André Ivanov, Res Saleh, Partha Pratim Pande

Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006

2005

Crosstalk bounded uncorrelated jitter (BUJ) for high-speed interconnects.

Andy Kuo, Roberto Rosales, Touraj Farahmand, Sassan Tabatabaei, André Ivanov

IEEE Trans. Instrum. Meas., 2005

Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures.

Partha Pratim Pande, Cristian Grecu, Michael Jones, André Ivanov, Resve A. Saleh

IEEE Trans. Computers, 2005

Timing analysis of network on chip architectures for MP-SoC platforms.

Cristian Grecu, Partha Pratim Pande, André Ivanov, Res Saleh

Microelectron. J., 2005

A Realistic Timing Test Model and Its Applications in High-Speed Interconnect Devices.

Baosheng Wang, Andy Kuo, Touraj Farahmand, André Ivanov, Yong B. Cho, Sassan Tabatabaei

J. Electron. Test., 2005

An Analog Circuit Fault Characterization Methodology.

Yvan Maidon, Thomas Zimmer, André Ivanov

J. Electron. Test., 2005

Design, Synthesis, and Test of Networks on Chips.

Partha Pratim Pande, Cristian Grecu, André Ivanov, Resve A. Saleh, Giovanni De Micheli

IEEE Des. Test Comput., 2005

Guest Editors' Introduction: The Network-on-Chip Paradigm in Practice and Research.

André Ivanov, Giovanni De Micheli

IEEE Des. Test Comput., 2005

SRAM Retention Testing: Zero Incremental Time Integration with March Algorithms.

Baosheng Wang, Yuejian Wu, Josh Yang, André Ivanov, Yervant Zorian

Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005

A DDJ calibration methodology for high-speed test and measurement equipments.

Touraj Farahmand, Sassan Tabatabaei, Freddy Ben-Zeev, André Ivanov

Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

A 4-bit 5 GS/s flash A/D converter in 0.18µm CMOS.

Samad Sheikhaei, Shahriar Mirabbasi, André Ivanov

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A 0.35µm CMOS comparator circuit for high-speed ADC applications.

Samad Sheikhaei, Shahriar Mirabbasi, André Ivanov

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Effect of traffic localization on energy dissipation in NoC-based interconnect.

Partha Pratim Pande, Cristian Grecu, Michael Jones, André Ivanov, Res Saleh

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Methodologies and Algorithms for Testing Switch-Based NoC Interconnects.

Cristian Grecu, Partha Pratim Pande, Baosheng Wang, André Ivanov, Res Saleh

Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005

A Fast Diagnosis Scheme for Distributed Small Embedded SRAMs.

Baosheng Wang, Yuejian Wu, André Ivanov

Proceedings of the 2005 Design, 2005

A retention-aware test power model for embedded SRAM.

Baosheng Wang, Josh Yang, Yuejian Wu, André Ivanov

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004

Indirect test architecture for SoC testing.

Mohsen Nahvi, André Ivanov

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Jitter Models for the Design and Test of Gbps-Speed Serial Interconnects.

Nelson Ou, Touraj Farahmand, Andy Kuo, Sassan Tabatabaei, André Ivanov

IEEE Des. Test Comput., 2004

Guest Editors' Introduction: Advances in VLSI Testing at MultiGbps Rates.

André Ivanov, Fabrizio Lombardi, Cecilia Metra

IEEE Des. Test Comput., 2004

Reducing Embedded SRAM Test Time under Redundancy Constraints.

Baosheng Wang, Josh Yang, James Cicalo, André Ivanov, Yervant Zorian

Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004

Sensing temperature in CMOS circuits for Thermal Testing.

Josep Altet, Antonio Rubio, M. Amine Salhi, Jose Luis Gálvez, Stefan Dilhaire, Ashish Syal, André Ivanov

Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004

Open Defects Detection within 6T SRAM Cells using a No Write Recovery Test Mode.

Josh Yang, Baosheng Wang, André Ivanov

Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

Jitter Models and Measurement Methods for High-Speed Serial Interconnects.

Andy Kuo, Touraj Farahmand, Nelson Ou, André Ivanov, Sassan Tabatabaei

Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

A Scalable Communication-Centric SoC Interconnect Architecture.

Cristian Grecu, Partha Pratim Pande, André Ivanov, Res Saleh

Proceedings of the 5th International Symposium on Quality of Electronic Design (ISQED 2004), 2004

Structured interconnect architecture: a solution for the non-scalability of bus-based SoCs.

Cristian Grecu, Partha Pratim Pande, André Ivanov, Res Saleh

Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004

Designs for Reducing Test Time of Distributed Small Embedded SRAMs.

Baosheng Wang, Yuejian Wu, André Ivanov

Proceedings of the 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 2004

2003

Test Technology Technical Council Newsletter.

André Ivanov

J. Electron. Test., 2003

Guest Editorial.

André Ivanov

J. Electron. Test., 2003

Thermal Testing of Analogue Integrated Circuits: A Case Study.

Josep Altet, André Ivanov, A. Wong

J. Electron. Test., 2003

An All-Digital DFT Scheme for Testing Catastrophic Faults in PLLs.

Florence Azaïs, Yves Bertrand, Michel Renovell, André Ivanov, Sassan Tabatabaei

IEEE Des. Test Comput., 2003

An Embedded Autonomous Scan-Based Results Analyzer (EARA) for SoC Cores.

Mohsen Nahvi, André Ivanov

Proceedings of the 21st IEEE VLSI Test Symposium (VTS 2003), 27 April, 2003

Reducing Test Time of Embedded SRAMs.

Baosheng Wang, Josh Yang, André Ivanov

Proceedings of the 11th IEEE International Workshop on Memory Technology, 2003

High-Throughput Switch-Based Interconnect for Future SoCs.

Partha Pratim Pande, Cristian Grecu, André Ivanov

Proceedings of the 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'03), 30 June, 2003

Design of a switch for network on chip applications.

Partha Pratim Pande, Cristian Grecu, André Ivanov, Res Saleh

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Analog IP design flow for SoC applications.

Mama Hamour, Resve A. Saleh, Shahriar Mirabbasi, André Ivanov

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Time Domain Multiplexed TAM: Implementation and Comparison.

Zahra Sadat Ebadi, André Ivanov

Proceedings of the 2003 Design, 2003

Yield, Overall Test Environment Timing Accuracy, and Defect Level Trade-Offs for High-Speed Interconnect Device Testing.

Baosheng Wang, Yong B. Cho, Sassan Tabatabaei, André Ivanov

Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

2002

CMOS Differential and Absolute Thermal Sensors.

Ashish Syal, Victor Lee, André Ivanov, Josep Altet

J. Electron. Test., 2002

Embedded Timing Analysis: A SoC Infrastructure.

Sassan Tabatabaei, André Ivanov

IEEE Des. Test Comput., 2002

Design of an Optimal Test Access Architecture under Power and Place-and-Route Constraints Using GA.

Zahra Sadat Ebadi, André Ivanov

Proceedings of the 3rd Latin American Test Workshop, 2002

An Embedded Core for Sub-Picosecond Timing Measurements.

Sassan Tabatabaei, André Ivanov

Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

Dedicated Autonomous Scan-Based Testing (DAST) for Embedded Cores.

Mohsen Nahvi, André Ivanov, Resve A. Saleh

Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

An Off-Chip Sensor Circuit for On-Line Transient Current Testing.

Bartomeu Alorda, André Ivanov, Jaume Segura

Proceedings of the 8th IEEE International On-Line Testing Workshop (IOLTW 2002), 2002

2001

On the detectability of CMOS floating gate transistor faults.

André Ivanov, Sumbal Rafiq, Michel Renovell, Florence Azaïs, Yves Bertrand

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

Test Technology Newsletter.

André Ivanov

J. Electron. Test., 2001

A packet switching communication-based test access mechanism for system chips.

Mohsen Nahvi, André Ivanov

Proceedings of the 6th European Test Workshop, 2001

Design of an Optimal Test Access Architecture Using a Genetic Algorithm.

Zahra Sadat Ebadi, André Ivanov

Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

2000

Catastrophic Short and Open Fault Detection in Bipolar CML Circuits: A Case Study.

André Ivanov, Vikram Devdas

J. Electron. Test., 2000

Biomedical ICs: What is Different about Testing those ICs?

Bapiraju Vinnakota, André Ivanov

Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000

Do I Need this Tool for My Chips to Work?

Fidel Muradali, André Ivanov

Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000

Defect Oriented Testing of an ECL/CMOS Level Converter Circuit.

Min-Hsing P. Chen, André Ivanov, Sassan Tabatabaei

Proceedings of the 1st Latin American Test Workshop, 2000

1999

A Current Integrator for BIST of Mixed-Signal ICs.

Sassan Tabatabaei, André Ivanov

Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999

Optimal conditions for Boolean and current detection of floating gate faults.

Michel Renovell, André Ivanov, Yves Bertrand, Florence Azaïs, Sumbal Rafiq

Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

A built-in current monitor for testing analog circuit blocks.

Sassan Tabatabaei, André Ivanov

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

1998

Testing for Floating Gates Defects in CMOS Circuits.

Sumbal Rafiq, André Ivanov, Sassan Tabatabaei, Michel Renovell

Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998

Non-Intrusive Testing of High-Speed CML Circuits.

Vikram Devdas, André Ivanov

Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998

A Methodology and Design for Effective Testing of Voltage-Controlled Oscillators (VCOs.

Florence Azaïs, André Ivanov, Michel Renovell, Yves Bertrand

Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998

1997

Power supply current monitoring techniques for testing PLLs.

Maneesha Dalmia, André Ivanov, Sassan Tabatabaei

Proceedings of the 6th Asian Test Symposium (ATS '97), 17-18 November 1997, 1997

1996

Programmable BIST Space Compactors.

André Ivanov, Barry K. Tsuji, Yervant Zorian

IEEE Trans. Computers, 1996

Panel Summaries.

Yervant Zorian, Tom Anderson, Yvon Savaria, Claude Thibeault, André Ivanov

IEEE Des. Test Comput., 1996

1995

Fast signature computation for BIST linear compactors.

D. Lambidonis, André Ivanov, Vinod K. Agarwal

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

Single-Reference Multiple Intermediate Signature (SREMIS) Analysis for BIST.

Yuejian Wu, André Ivanov

IEEE Trans. Computers, 1995

A quasi-optimal scheduling of intermediate signatures for multiple signature analysis compaction testing schemes.

D. Lambidonis, Vinod K. Agarwal, André Ivanov, Dhiren Xavier

J. Electron. Test., 1995

Reducing Hardware with Fuzzy Multiple Signature Analysis.

Yuejian Wu, André Ivanov

IEEE Des. Test Comput., 1995

Fault Simulation of an OTA Biquadratic Filter.

Andrew Bishop, André Ivanov

Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

1994

On minimizing aliasing in scan-based compaction.

Slawomir Pilarski, André Ivanov, Tiko Kameda

J. Electron. Test., 1994

On the Testability of CMOS Feedback Amplifiers.

Andrew J. Bishop, André Ivanov

Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1994

1993

Sequential faults and aliasing.

Slawomir Pilarski, Tiko Kameda, André Ivanov

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993

Notes on Multiple Input Signature Analysis.

Tiko Kameda, Slawomir Pilarski, André Ivanov

IEEE Trans. Computers, 1993

Minimal hardware multiple signature analysis for BIST.

Yuejian Wu, André Ivanov

Proceedings of the 11th IEEE VLSI Test Symposium (VTS'93), 1993

Programmable Space Compaction for BIST.

Yervant Zorian, André Ivanov

Proceedings of the Digest of Papers: FTCS-23, 1993

1992

Computing the probability of undetected error for shortened cyclic codes.

Vinod K. Agarwal, André Ivanov

IEEE Trans. Commun., 1992

Using an asymmetric error model to study aliasing in signature analysis registers.

Dhiren Xavier, Robert C. Aitken, André Ivanov, Vinod K. Agarwal

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992

Count-based BIST compaction schemes and aliasing probability computation.

André Ivanov, Yervant Zorian

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992

An Effective BIST Scheme for ROM's.

Yervant Zorian, André Ivanov

IEEE Trans. Computers, 1992

Performance of signature analysis: a survey of bounds, exact, and heuristic algorithms.

André Ivanov, Slawomir Pilarski

Integr., 1992

Accelerated path delay fault simulation.

Yuejian Wu, André Ivanov

Proceedings of the 10th IEEE VLSI Test Symposium (VTS'92), 1992

1991

Iterative algorithms for computing aliasing probabilities.

André Ivanov, Corot W. Starke, Vinod K. Agarwal, Wilfried Daehn, Matthias Gruetzner, Tom W. Williams

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991

Fast Signature Computation for Linear Compactors.

D. Lambidonis, André Ivanov, Vinod K. Agarwal

Proceedings of the Proceedings IEEE International Test Conference 1991, 1991

1990

EEODM: An effective BIST scheme for ROMs.

Yervant Zorian, André Ivanov

Proceedings of the Proceedings IEEE International Test Conference 1990, 1990

Computing the Error Escape Probability in Count-Based Compaction Schemes.

André Ivanov, Yervant Zorian

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990

1989

An analysis of the probabilistic behavior of linear feedback signature registers.

André Ivanov, Vinod K. Agarwal

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989

: Experiments on Aliasing in Signature Analysis Registers.

Dhiren Xavier, Robert C. Aitken, André Ivanov, Vinod K. Agarwal

Proceedings of the Proceedings International Test Conference 1989, 1989

1988

Dynamic testability measures for ATPG.

André Ivanov, Vinod K. Agarwal

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988

On Multiple Fault Coverage and Aliasing Probability Measures.

Henry Cox, André Ivanov, Vinod K. Agarwal, Janusz Rajski

Proceedings of the Proceedings International Test Conference 1988, 1988

An iterative technique for calculating aliasing probability of linear feedback signature registers.

André Ivanov, Vinod K. Agarwal

Proceedings of the Eighteenth International Symposium on Fault-Tolerant Computing, 1988

1986

Testability Measures : What Do They Do for ATPG ?

André Ivanov, Vinod K. Agarwal

Proceedings of the Proceedings International Test Conference 1986, 1986