William George Osborne

According to our database1, William George Osborne authored at least 9 papers between 2006 and 2011.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2011
Data representation optimisation for reconfigurable hardware design.
PhD thesis, 2011

Energy Reduction by Systematic Run-Time Reconfigurable Hardware Deactivation.
Trans. High Perform. Embed. Archit. Compil., 2011

2009
Accelerating Seismic Computations Using Customized Number Representations on FPGAs.
EURASIP J. Embed. Syst., 2009

A high-level compilation toolchain for heterogeneous systems.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009

2008
Reconfigurable design with clock gating.
Proceedings of the 2008 International Conference on Embedded Computer Systems: Architectures, 2008

Power-Aware and Branch-Aware Word-Length Optimization.
Proceedings of the 16th IEEE International Symposium on Field-Programmable Custom Computing Machines, 2008

2007
Instrumented Multi-Stage Word-Length Optimization.
Proceedings of the 2007 International Conference on Field-Programmable Technology, 2007

Automatic Accuracy-Guaranteed Bit-Width Optimization for Fixed and Floating-Point Systems.
Proceedings of the FPL 2007, 2007

2006
UNITE: Uniform Hardware-Based Network Intrusion deTection Engine.
Proceedings of the Reconfigurable Computing: Architectures and Applications, 2006


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